mirror of https://github.com/YosysHQ/yosys.git
64 lines
1.3 KiB
Plaintext
64 lines
1.3 KiB
Plaintext
read_verilog <<EOT
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module peepopt_shiftmul_0 #(parameter N=3, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output [W-1:0] o);
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assign o = i[s*W+:W];
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endmodule
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EOT
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prep -nokeepdc
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equiv_opt -assert peepopt
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design -load postopt
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clean
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select -assert-count 1 t:$shiftx
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select -assert-count 0 t:$shiftx t:* %D
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####################
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design -reset
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read_verilog <<EOT
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module peepopt_shiftmul_1 (output [7:0] y, input [2:0] w);
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assign y = 1'b1 >> (w * (3'b110));
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endmodule
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EOT
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prep -nokeepdc
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equiv_opt -assert peepopt
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design -load postopt
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clean
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select -assert-count 1 t:$shr
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select -assert-count 1 t:$mul
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select -assert-count 0 t:$shr t:$mul %% t:* %D
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####################
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design -reset
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read_verilog <<EOT
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module peepopt_muldiv_0(input [1:0] i, output [1:0] o);
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wire [3:0] t;
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assign t = i * 3;
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assign o = t / 3;
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endmodule
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EOT
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prep -nokeepdc
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equiv_opt -assert peepopt
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design -load postopt
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clean
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select -assert-count 0 t:*
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####################
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design -reset
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read_verilog <<EOT
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module peepopt_dffmuxext_signed(input clk, ce, input signed [1:0] i, output reg signed [3:0] o);
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always @(posedge clk) if (ce) o <= i;
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endmodule
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EOT
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prep -nokeepdc
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equiv_opt peepopt
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design -load postopt
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clean
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select -assert-count 1 t:$dff r:WIDTH=2 %i
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select -assert-count 1 t:$mux r:WIDTH=2 %i
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select -assert-count 0 t:$dff t:$mux %% t:* %D
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