Eddie Hung 5189695362 read_verilog cells_box.v before techmap		2019-04-16 12:41:56 -07:00
..
achronix	Reduce amount of trailing whitespace in code base	2019-02-28 14:58:11 -08:00
anlogic	Reduce amount of trailing whitespace in code base	2019-02-28 14:58:11 -08:00
common	synth to take -abc9 argument	2019-02-20 11:08:49 -08:00
coolrunner2	Unify usage of noflatten among architectures	2019-01-04 11:37:25 +01:00
easic	Fix typographical and grammatical errors and inconsistencies.	2019-01-02 13:12:17 +00:00
ecp5	ecp5: Demote conflicting FF init values to a warning	2019-03-04 11:26:20 +00:00
gowin	Reduce amount of trailing whitespace in code base	2019-02-28 14:58:11 -08:00
greenpak4	techlibs/greenpak4/cells_map.v: Harmonize whitespace within lut module	2019-02-26 09:40:46 -08:00
ice40	Merge branch 'master' into xaig	2019-04-08 16:31:59 -07:00
intel	Fixing issues in CycloneV cell sim	2019-04-11 19:59:03 -05:00
sf2	Add link to SF2 / igloo2 macro library guide	2019-03-07 09:08:26 -08:00
xilinx	read_verilog cells_box.v before techmap	2019-04-16 12:41:56 -07:00
.gitignore	added .gitignore files	2013-01-05 11:19:11 +01:00