mirror of https://github.com/YosysHQ/yosys.git
84 lines
4.4 KiB
Verilog
84 lines
4.4 KiB
Verilog
// TODO add these DFF types
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// Primitive Description
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// DFFSE D Flip-Flop with Clock Enable and Synchronous Set
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// DFFRE D Flip-Flop with Clock Enable and Synchronous Reset
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// DFFNS D Flip-Flop with Negative-Edge Clock and Synchronous Set
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// DFFNSE D Flip-Flop with Negative-Edge Clock,Clock Enable,and Synchronous Set
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// DFFNR D Flip-Flop with Negative-Edge Clock and Synchronous Reset
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// DFFNRE D Flip-Flop with Negative-Edge Clock,Clock Enable, and Synchronous Reset
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// DFFNP D Flip-Flop with Negative-Edge Clock and Asynchronous Preset
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// DFFNPE D Flip-Flop with Negative-Edge Clock,Clock Enable, and Asynchronous Preset
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// DFFNC D Flip-Flop with Negative-Edge Clock and Asynchronous Clear
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// DFFNCE D Flip-Flop with Negative-Edge Clock,Clock Enable and Asynchronous Clear
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//TODO all DFF* have INIT
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// DFFN D Flip-Flop with Negative-Edge Clock
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module \$_DFF_N_ (input D, C, output Q); DFFN _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); endmodule
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// DFF D Flip-Flop
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module \$_DFF_P_ #(parameter INIT = 1'b0) (input D, C, output Q); DFF #(.INIT(INIT)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); endmodule
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// DFFE D Flip-Flop with Clock Enable
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module \$_DFFE_PP_ (input D, C, E, output Q); DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E)); endmodule
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module \$_DFFE_PN_ (input D, C, E, output Q); DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(!E)); endmodule
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// DFFNE D Flip-Flop with Negative-Edge Clock and Clock Enable
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module \$_DFFE_NP_ (input D, C, E, output Q); DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E)); endmodule
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module \$_DFFE_NN_ (input D, C, E, output Q); DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(!E)); endmodule
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// DFFR D Flip-Flop with Synchronous Reset
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module \$__DFFS_PN0_ (input D, C, R, output Q); DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R)); endmodule
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module \$__DFFS_PP0_ (input D, C, R, output Q); DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R)); endmodule
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// DFFS D Flip-Flop with Synchronous Set
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module \$__DFFS_PN1_ (input D, C, S, output Q); DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!S)); endmodule
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module \$__DFFS_PP1_ (input D, C, S, output Q); DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(S)); endmodule
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// DFFP D Flip-Flop with Asynchronous Preset
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module \$_DFF_PP1_ (input D, C, R, output Q); DFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R)); endmodule
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module \$_DFF_PN1_ (input D, C, R, output Q); DFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R)); endmodule
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// DFFC D Flip-Flop with Asynchronous Clear
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module \$_DFF_PP0_ (input D, C, R, output Q); DFFC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R)); endmodule
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module \$_DFF_PN0_ (input D, C, R, output Q); DFFC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R)); endmodule
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// DFFPE D Flip-Flop with Clock Enable and Asynchronous Preset
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module \$__DFFE_PP1_ (input D, C, R, E, output Q); DFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E)); endmodule
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module \$__DFFE_PN1_ (input D, C, R, E, output Q); DFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R), .CE(E)); endmodule
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// DFFCE D Flip-Flop with Clock Enable and Asynchronous Clear
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module \$__DFFE_PP0_ (input D, C, R, E, output Q); DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E)); endmodule
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module \$__DFFE_PN0_ (input D, C, R, E, output Q); DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R), .CE(E)); endmodule
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module \$_MUX_ (input A, B, S, output Y); MUX2 _TECHMAP_REPLACE_ (.I0(A), .I1(B), .S0(S), .O(Y)); endmodule
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module \$_MUX4_ (input A, B, C, D, S, T, output Y); MUX4 _TECHMAP_REPLACE_ (.I0(A), .I1(B), .I2(C), .I3(D), .S0(S), .S1(T), .O(Y)); endmodule
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module \$lut (A, Y);
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parameter WIDTH = 0;
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parameter LUT = 0;
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input [WIDTH-1:0] A;
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output Y;
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generate
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if (WIDTH == 1) begin
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LUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
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.I0(A[0]));
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end else
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if (WIDTH == 2) begin
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LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
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.I0(A[0]), .I1(A[1]));
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end else
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if (WIDTH == 3) begin
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LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
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.I0(A[0]), .I1(A[1]), .I2(A[2]));
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end else
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if (WIDTH == 4) begin
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LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
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.I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));
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end else begin
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wire _TECHMAP_FAIL_ = 1;
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end
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endgenerate
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endmodule
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