mirror of https://github.com/YosysHQ/yosys.git
253 lines
7.3 KiB
TeX
253 lines
7.3 KiB
TeX
\chapter{RTLIL Text Representation}
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\label{chapter:textrtlil}
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% Stolen from stackexchange: calculate indent based on given keyword,
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% with some nice hrules added in.
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\newlength{\myl}
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\newenvironment{indentgrammar}[1]
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{\vspace{0.5cm}\hrule
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\setlength{\myl}{\widthof{#1}+2em}
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\grammarindent\the\myl
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\begin{grammar}}
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{\end{grammar}
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\hrule}
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This appendix documents the text representation of RTLIL in extended Backus-Naur form (EBNF).
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The grammar is not meant to represent semantic limitations. For example, processes must contain exactly one switch statement, but the grammar allows zero or more than one. That is, the grammar is "permissive", and later stages of processing perform more rigorous checks.
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The grammar is also not meant to represent the exact grammar used in the RTLIL frontend, since that grammar is specific to processing by lex and yacc, and is somewhat less understandable than simple EBNF notation.
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\section{Lexical elements}
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\subsection{Identifiers}
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There are three types of identifiers in RTLIL:
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\begin{itemize}
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\item Publically visible identifiers
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\item Auto-generated identifiers
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\item Dotted numeric identifiers
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\end{itemize}
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\begin{indentgrammar}{<autogen-id>}
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<id> ::= <public-id> | <autogen-id> | <dotted-id>
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<public-id> ::= "\textbackslash" <nonws>$+$
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<autogen-id> ::= "\textdollar" <nonws>$+$
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<dotted-id> ::= "." <decimal-digit>$+$
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\end{indentgrammar}
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\subsection{Values}
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A \textit{value} consists of a width in bits and a bit representation, most significant bit first. Bits may be any of:
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\begin{itemize}
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\item \texttt{0}: A logic zero value
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\item \texttt{1}: A logic one value
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\item \texttt{x}: An unknown logic value
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\item \texttt{z}: A high-impedance value (or don't care in case patterns)
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\item \texttt{m}: A marked bit (internal use only)
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\item \texttt{-}: A don't care value
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\end{itemize}
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An \textit{integer} is simply a signed integer value in decimal format.
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\begin{indentgrammar}{<binary-digit>}
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<value> ::= <decimal-digit>$+$ \texttt{\textbf{'}} <binary-digit>$*$
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<binary-digit> ::= "0" | "1" | "x" | "z" | "m" | "-"
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<integer> ::= "-"$?$ <decimal-digit>$+$
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\end{indentgrammar}
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\subsection{Strings}
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A string is a series of characters delimited by double-quote characters. Within a string, certain escapes can be used:
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\begin{itemize}
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\item \texttt{\textbackslash n}: A newline
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\item \texttt{\textbackslash t}: A tab
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\item \texttt{\textbackslash \textit{ooo}}: A character specified as a one, two, or three digit octal value
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\end{itemize}
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All other characters may be escaped by a backslash, and become the following character. Thus:
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\begin{itemize}
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\item \texttt{\textbackslash \textbackslash}: A backslash
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\item \texttt{\textbackslash \"}: A double-quote
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\item \texttt{\textbackslash r}: An 'r' character
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\end{itemize}
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\subsection{Comments}
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A comment starts with a \texttt{\textbf{\#}} character and proceeds to the end of the line. All comments are ignored.
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\section{File}
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A file consists of zero or more designs. A design may be a module, an attribute statement, or an autoindex statement.
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Note that in general, statements are terminated by an end of line.
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\begin{indentgrammar}{<design>}
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<file> ::= <design>$*$
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<design> ::= <module> | <attr-stmt> | <autoidx-stmt>
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\end{indentgrammar}
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\subsection{Modules}
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A module consists of zero or more module statements.
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\begin{indentgrammar}{<module-stmt>}
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<module> ::= "module" <id> <eol> <module-stmt>$*$
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<module-stmt> ::=
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<param-stmt>
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\alt <attr-stmt>
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\alt <wire-stmt>
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\alt <memory-stmt>
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\alt <cell-stmt>
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\alt <proc-stmt>
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\alt <conn-stmt>
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\end{indentgrammar}
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\subsection{Signal specifications}
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A signal is anything that can be applied to a cell port, i.e. a constant value, all bits or a selection of bits from a wire, or concatenations of those.
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See Sec.~\ref{sec:rtlil_sigspec} for an overview of signal specifications.
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\begin{indentgrammar}{<sigspec>}
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<sigspec> ::=
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<constant>
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\alt <wire-id>
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\alt <sigspec> "[" <integer> (":" <integer>)$?$ "]"
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\alt "\{" <sigspec>$*$ "\}"
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\end{indentgrammar}
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\subsection{Connection statements}
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Declares a connection between the given signals.
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\begin{indentgrammar}{<conn-stmt>}
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<conn-stmt> ::= "connect" <sigspec> <sigspec> <eol>
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\end{indentgrammar}
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\subsection{Attribute statements}
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Declares an attribute with the given identifier and value for the following non-attribute statement.
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\begin{indentgrammar}{<attr-stmt>}
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<attr-stmt> ::= "attribute" <id> <constant> <eol>
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<constant> ::= <value> | <integer> | <string>
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\end{indentgrammar}
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\subsection{Autoindex statements}
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The function of this statement is currently undocumented.
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\begin{indentgrammar}{<autoidx-stmt>}
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<autoidx-stmt> ::= "autoidx" <integer> <eol>
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\end{indentgrammar}
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\subsection{Parameter statements}
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Declares a parameter with the given identifier for the enclosing module, optionally with the given default value.
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\begin{indentgrammar}{<param-stmt>}
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<param-stmt> ::= "parameter" <id> <constant>$?$ <eol>
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\end{indentgrammar}
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\subsection{Wire statements}
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Declares a wire with the given identifier in the enclosing module, with options.
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See Sec.~\ref{sec:rtlil_cell_wire} for an overview of wires.
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\begin{indentgrammar}{<wire-option>}
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<wire-stmt> ::= "wire" <wire-option>$*$ <wire-id> <eol>
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<wire-id> ::= <id>
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<wire-option> ::=
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"width" <integer>
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\alt "offset" <integer>
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\alt "input" <integer>
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\alt "output" <integer>
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\alt "inout" <integer>
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\alt "upto"
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\alt "signed"
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\end{indentgrammar}
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\subsection{Memory statements}
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Declares a memory with the given identifier in the enclosing module, with options.
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See Sec.~\ref{sec:rtlil_memory} for an overview of memory cells, and Sec.~\ref{sec:memcells} for details about memory cell types.
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\begin{indentgrammar}{<memory-option>}
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<memory-stmt> ::= "memory" <memory-option>$*$ <id> <eol>
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<memory-option> ::=
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"width" <integer>
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\alt "size" <integer>
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\alt "offset" <integer>
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\end{indentgrammar}
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\subsection{Cell statements}
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Declares a cell with the given identifier in the enclosing module.
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See Chap.~\ref{chapter:celllib} for a detailed list of cell types.
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\begin{indentgrammar}{<cell-body-stmt>}
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<cell-stmt> ::= "cell" <cell-id> <cell-type> <eol> <cell-body-stmt> "end" <eol>
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<cell-id> ::= <id>
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<cell-type> ::= <id>
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<cell-body-stmt> ::=
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"parameter" ("signed" | "real")$?$ <id> <constant> <eol>
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\alt "connect" <id> <sigspec> <eol>
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\end{indentgrammar}
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\subsection{Process statements}
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Declares a process with the given identifier in the enclosing module.
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See Sec.~\ref{sec:rtlil_process} for an overview of processes.
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\begin{indentgrammar}{<switch-element>}
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<proc-stmt> ::= "process" <id> <eol> <case-stmt>$*$ <sync-stmt>$*$ "end" <eol>
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<case-stmt> ::= <attr-stmt> | <switch-stmt> | <assign-stmt>
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<switch-stmt> ::= "switch" <sigspec> <eol> <attr-stmt>$*$ <switch-element>$*$ "end" <eol>
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<switch-element> ::= "case" <compare>$?$ <eol> <case-stmt>$*$
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<compare> ::= <sigspec> ("," <sigspec>)$*$
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<sync-stmt> ::=
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"sync" <sync-type> <sigspec> <eol> <update-stmt>$*$
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\alt "sync" "always" <eol> <update-stmt>$*$
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\alt "sync" "global" <eol> <update-stmt>$*$
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\alt "sync" "init" <eol> <update-stmt>$*$
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<sync-type> ::= "low" | "high" | "posedge" | "negedge" | "edge"
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<assign-stmt> ::= "assign" <dest-sigspec> <src-sigspec> <eol>
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<update-stmt> ::= "update" <dest-sigspec> <src-sigspec> <eol>
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<dest-sigspec> ::= <sigspec>
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<src-sigspec> ::= <sigspec>
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\end{indentgrammar}
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