mirror of https://github.com/YosysHQ/yosys.git
510d137996
These are useful for formal verification with SBY where they can be used to display solver chosen `rand const reg` signals and signals derived from those. The previous error message for non-constant initial $display statements is downgraded to a log message. Constant initial $display statements will be shown both during elaboration and become part of the RTLIL so that the `sim` output is complete. |
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| .. | ||
| Makefile.inc | ||
| ast.cc | ||
| ast.h | ||
| ast_binding.cc | ||
| ast_binding.h | ||
| dpicall.cc | ||
| genrtlil.cc | ||
| simplify.cc | ||