mirror of https://github.com/YosysHQ/yosys.git
210 lines
6.7 KiB
C++
210 lines
6.7 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/sigtools.h"
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#include "kernel/rtlil.h"
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#include "kernel/log.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct ConnwrappersWorker
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{
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struct portdecl_t {
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// key: celltype, portname;
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std::string widthparam, signparam;
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bool is_signed;
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};
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std::set<RTLIL::IdString> decl_celltypes;
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std::map<std::pair<RTLIL::IdString, RTLIL::IdString>, portdecl_t> decls;
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void add_port(std::string celltype, std::string portname, std::string widthparam, std::string signparam)
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{
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std::pair<std::string, std::string> key(RTLIL::escape_id(celltype), RTLIL::escape_id(portname));
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decl_celltypes.insert(key.first);
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if (decls.count(key))
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log_cmd_error("Duplicate port decl: %s %s\n", celltype.c_str(), portname.c_str());
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portdecl_t decl;
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decl.widthparam = RTLIL::escape_id(widthparam);
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decl.signparam = RTLIL::escape_id(signparam);
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decl.is_signed = false;
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decls[key] = decl;
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}
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void add_port(std::string celltype, std::string portname, std::string widthparam, bool is_signed)
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{
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std::pair<std::string, std::string> key(RTLIL::escape_id(celltype), RTLIL::escape_id(portname));
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decl_celltypes.insert(key.first);
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if (decls.count(key))
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log_cmd_error("Duplicate port decl: %s %s\n", celltype.c_str(), portname.c_str());
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portdecl_t decl;
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decl.widthparam = RTLIL::escape_id(widthparam);
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decl.is_signed = is_signed;
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decls[key] = decl;
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}
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void work(RTLIL::Design *design, RTLIL::Module *module)
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{
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std::map<RTLIL::SigBit, std::pair<bool, RTLIL::SigSpec>> extend_map;
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SigMap sigmap(module);
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for (auto &it : module->cells_)
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{
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RTLIL::Cell *cell = it.second;
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if (!decl_celltypes.count(cell->type))
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continue;
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for (auto &conn : cell->connections())
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{
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std::pair<RTLIL::IdString, RTLIL::IdString> key(cell->type, conn.first);
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if (!decls.count(key))
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continue;
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portdecl_t &decl = decls.at(key);
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if (!cell->parameters.count(decl.widthparam))
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continue;
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if (!decl.signparam.empty() && !cell->parameters.count(decl.signparam))
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continue;
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int inner_width = cell->parameters.at(decl.widthparam).as_int();
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int outer_width = conn.second.size();
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bool is_signed = decl.signparam.empty() ? decl.is_signed : cell->parameters.at(decl.signparam).as_bool();
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if (inner_width >= outer_width)
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continue;
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RTLIL::SigSpec sig = sigmap(conn.second);
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extend_map[sig.extract(inner_width - 1, 1)] = std::pair<bool, RTLIL::SigSpec>(is_signed,
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sig.extract(inner_width, outer_width - inner_width));
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}
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}
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for (auto &it : module->cells_)
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{
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RTLIL::Cell *cell = it.second;
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if (!design->selected(module, cell))
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continue;
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for (auto &conn : cell->connections_)
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{
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std::vector<RTLIL::SigBit> sigbits = sigmap(conn.second).to_sigbit_vector();
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RTLIL::SigSpec old_sig;
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for (size_t i = 0; i < sigbits.size(); i++)
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{
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if (!extend_map.count(sigbits[i]))
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continue;
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bool is_signed = extend_map.at(sigbits[i]).first;
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RTLIL::SigSpec extend_sig = extend_map.at(sigbits[i]).second;
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int extend_width = 0;
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RTLIL::SigBit extend_bit = is_signed ? sigbits[i] : RTLIL::SigBit(RTLIL::State::S0);
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while (extend_width < extend_sig.size() && i + extend_width + 1 < sigbits.size() &&
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sigbits[i + extend_width + 1] == extend_bit) extend_width++;
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if (extend_width == 0)
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continue;
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if (old_sig.size() == 0)
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old_sig = conn.second;
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conn.second.replace(i+1, extend_sig.extract(0, extend_width));
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i += extend_width;
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}
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if (old_sig.size())
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log("Connected extended bits of %s.%s:%s: %s -> %s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name),
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RTLIL::id2cstr(conn.first), log_signal(old_sig), log_signal(conn.second));
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}
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}
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}
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};
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struct ConnwrappersPass : public Pass {
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ConnwrappersPass() : Pass("connwrappers", "replace undef values with defined constants") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" connwrappers [options] [selection]\n");
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log("\n");
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log("Wrappers are used in coarse-grain synthesis to wrap cells with smaller ports\n");
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log("in wrapper cells with a (larger) constant port size. I.e. the upper bits\n");
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log("of the wrapper outut are signed/unsigned bit extended. This command uses this\n");
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log("knowlege to rewire the inputs of the driven cells to match the output of\n");
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log("the driving cell.\n");
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log("\n");
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log(" -signed <cell_type> <port_name> <width_param>\n");
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log(" -unsigned <cell_type> <port_name> <width_param>\n");
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log(" consider the specified signed/unsigned wrapper output\n");
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log("\n");
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log(" -port <cell_type> <port_name> <width_param> <sign_param>\n");
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log(" use the specified parameter to decide if signed or unsigned\n");
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log("\n");
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log("The options -signed, -unsigned, and -port can be specified multiple times.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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ConnwrappersWorker worker;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-signed" && argidx+3 < args.size()) {
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worker.add_port(args[argidx+1], args[argidx+2], args[argidx+3], true);
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argidx += 3;
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continue;
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}
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if (args[argidx] == "-unsigned" && argidx+3 < args.size()) {
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worker.add_port(args[argidx+1], args[argidx+2], args[argidx+3], false);
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argidx += 3;
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continue;
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}
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if (args[argidx] == "-port" && argidx+4 < args.size()) {
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worker.add_port(args[argidx+1], args[argidx+2], args[argidx+3], args[argidx+4]);
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argidx += 4;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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log_header("Executing CONNWRAPPERS pass (connect extended ports of wrapper cells).\n");
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for (auto &mod_it : design->modules_)
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if (design->selected(mod_it.second))
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worker.work(design, mod_it.second);
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}
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} ConnwrappersPass;
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PRIVATE_NAMESPACE_END
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