mirror of https://github.com/YosysHQ/yosys.git
107 lines
3.9 KiB
Plaintext
107 lines
3.9 KiB
Plaintext
# ========================================================
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# throw in some extra text to match what we expect if we were opening an
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# interactive terminal
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log $ yosys fifo.v
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log
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log -- Parsing `fifo.v' using frontend ` -vlog2k' --
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read_verilog -defer fifo.v
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# turn command echoes on to use the log output as a console session
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echo on
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hierarchy -top addr_gen
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select -set new_cells t:*
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show -color maroon3 @new_cells -notitle -format dot -prefix addr_gen_hier
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# ========================================================
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proc
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select -set new_cells t:$mux t:*dff
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show -color maroon3 @new_cells -notitle -format dot -prefix addr_gen_proc
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# ========================================================
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opt_clean
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show -notitle -format dot -prefix addr_gen_clean
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# ========================================================
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design -reset
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read_verilog fifo.v
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hierarchy -check -top fifo
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proc
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show -color maroon3 c:fifo_reader -notitle -format dot -prefix rdata_proc o:rdata %ci*
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# ========================================================
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flatten;;
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show -notitle -format dot -prefix rdata_flat o:rdata %ci*
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# ========================================================
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opt_dff
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select -set new_cells t:$adffe
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show -color maroon3 @new_cells -notitle -format dot -prefix rdata_adffe o:rdata %ci*
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# ========================================================
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memory_dff
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select -set new_cells t:$memrd_v2
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show -color maroon3 @new_cells -notitle -format dot -prefix rdata_memrdv2 o:rdata %ci*
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# ========================================================
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alumacc
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select -set new_cells t:$alu t:$macc
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show -color maroon3 @new_cells -notitle -format dot -prefix rdata_alumacc o:rdata %ci*
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# ========================================================
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design -reset
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read_verilog fifo.v
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synth_ice40 -top fifo -run begin:map_ram
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select -set new_cells t:$mem_v2
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select -set rdata_path @new_cells %ci*:-$mem_v2[WR_DATA,WR_ADDR,WR_EN] @new_cells %co* %%
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show -color maroon3 @new_cells -notitle -format dot -prefix rdata_coarse @rdata_path
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# turn command echoes off to avoid randomly generated abc file names
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echo off
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# ========================================================
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synth_ice40 -top fifo -run map_ram:map_ffram
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select -set new_cells t:SB_RAM40_4K
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select -set rdata_path @new_cells %ci*:-SB_RAM40_4K[WDATA,WADDR,WE] @new_cells %co* %%
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show -color maroon3 @new_cells -notitle -format dot -prefix rdata_map_ram @rdata_path
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# ========================================================
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synth_ice40 -top fifo -run map_ffram:map_gates
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select -set new_cells t:SB_RAM40_4K
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select -set rdata_path @new_cells %ci*:-SB_RAM40_4K[WDATA,WADDR,WE] @new_cells %co* %%
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show -color maroon3 @new_cells -notitle -format dot -prefix rdata_map_ffram @rdata_path
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# ========================================================
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synth_ice40 -top fifo -run map_gates:map_ffs
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select -set new_cells t:SB_RAM40_4K
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select -set rdata_path @new_cells %ci*:-SB_RAM40_4K[WDATA,WADDR,WE] @new_cells %co* %%
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show -color maroon3 @new_cells -notitle -format dot -prefix rdata_map_gates @rdata_path
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# ========================================================
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synth_ice40 -top fifo -run map_ffs:map_luts
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select -set new_cells t:SB_RAM40_4K
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select -set rdata_path @new_cells %ci*:-SB_RAM40_4K[WDATA,WADDR,WE] @new_cells %co* %%
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show -color maroon3 @new_cells -notitle -format dot -prefix rdata_map_ffs @rdata_path
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# ========================================================
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synth_ice40 -top fifo -run map_luts:map_cells
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select -set new_cells t:SB_RAM40_4K
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select -set rdata_path @new_cells %ci*:-SB_RAM40_4K[WDATA,WADDR,WE] @new_cells %co* %%
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show -color maroon3 @new_cells -notitle -format dot -prefix rdata_map_luts @rdata_path
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# ========================================================
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synth_ice40 -top fifo -run map_cells:
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select -set new_cells t:SB_RAM40_4K
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select -set rdata_path @new_cells %ci*:-SB_RAM40_4K[WDATA,WADDR,WE] @new_cells %co* %%
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show -color maroon3 @new_cells -notitle -format dot -prefix rdata_map_cells @rdata_path
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