yosys/techlibs/common
Eddie Hung b6a1f627b5 Merge remote-tracking branch 'origin/master' into eddie/shiftx2mux 2020-02-05 10:47:31 -08:00
..
.gitignore Added first help messages for cell types 2015-10-14 16:27:42 +02:00
Makefile.inc Move from +/shiftx2mux.v into +/techmap.v; cleanup 2020-01-21 15:19:41 -08:00
adff2dff.v Added adff2dff.v (for techmap -share_map) 2014-08-07 16:14:38 +02:00
cellhelp.py Progress on cell help messages 2015-10-17 02:35:19 +02:00
cells.lib Added cells.lib 2015-01-16 15:50:42 +01:00
cmp2lut.v Do not map $eq and $ne in cmp2lut, only proper arithmetic cmp 2019-11-11 15:07:29 +01:00
dff2ff.v Add dff2ff.v techmap file 2017-05-31 11:45:58 +02:00
gate2lut.v gate2lut: new techlib, for converting Yosys gates to FPGA LUTs. 2018-12-05 17:13:27 +00:00
mul2dsp.v Missing (* mul2dsp *) for sliceB 2019-09-27 14:21:47 -07:00
pmux2mux.v Added techlibs/common/pmux2mux.v 2014-01-17 20:06:15 +01:00
prep.cc Add "wreduce -keepdc", fixes #1016 2019-05-20 15:36:13 +02:00
simcells.v Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs 2019-08-06 04:47:55 +02:00
simlib.v Reformat so it shows up/looks nice when "help $alu" and "help $alu+" 2019-08-09 12:33:39 -07:00
synth.cc Missing newline 2019-08-20 20:37:52 -07:00
techmap.v Explicitly create separate $mux cells 2020-01-21 16:49:34 -08:00