yosys/tests/arch/intel_alm
Marcelina Kościelnicka 50d532f01c techmap/shift_shiftx: Remove the "shiftx2mux" special path.
Our techmap rules for $shift and $shiftx cells contained a special path
that aimed to decompose the shift LSB-first instead of MSB-first in
select cases that come up in pmux lowering.  This path was needlessly
overcomplicated and contained bugs.

Instead of doing that, just switch over the main path to iterate
LSB-first (except for the specially-handled MSB for signed shifts
and overflow handling).  This also makes the code consistent with
shl/shr/sshl/sshr cells, which are already decomposed LSB-first.

Fixes #2346.
2020-08-20 12:44:09 +02:00
..
.gitignore Add missing .gitignore file 2020-06-04 22:25:47 +02:00
add_sub.ys intel_alm: add Cyclone 10 GX tests 2020-07-05 21:36:38 +02:00
adffs.ys Replace opt_rmdff with opt_dff. 2020-08-07 13:21:03 +02:00
blockram.ys intel_alm: direct M10K instantiation 2020-07-27 15:39:06 +02:00
counter.ys intel_alm: add Cyclone 10 GX tests 2020-07-05 21:36:38 +02:00
dffs.ys intel_alm: add Cyclone 10 GX tests 2020-07-05 21:36:38 +02:00
fsm.ys Replace opt_rmdff with opt_dff. 2020-08-07 13:21:03 +02:00
logic.ys intel_alm: add Cyclone 10 GX tests 2020-07-05 21:36:38 +02:00
lutram.ys intel_alm: add Cyclone 10 GX tests 2020-07-05 21:36:38 +02:00
mul.ys intel_alm: DSP inference 2020-07-05 05:39:20 +02:00
mux.ys techmap/shift_shiftx: Remove the "shiftx2mux" special path. 2020-08-20 12:44:09 +02:00
quartus_ice.ys intel_alm: add Cyclone 10 GX tests 2020-07-05 21:36:38 +02:00
run-test.sh synth_intel_alm: alternative synthesis for Intel FPGAs 2020-04-15 11:40:41 +02:00
shifter.ys intel_alm: add Cyclone 10 GX tests 2020-07-05 21:36:38 +02:00
tribuf.ys intel_alm: add Cyclone 10 GX tests 2020-07-05 21:36:38 +02:00