mirror of https://github.com/YosysHQ/yosys.git
78 lines
2.6 KiB
C++
78 lines
2.6 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifdef YOSYS_ENABLE_VERIFIC
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#include "DataBase.h"
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YOSYS_NAMESPACE_BEGIN
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extern int verific_verbose;
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extern pool<int> verific_sva_prims;
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struct VerificImporter;
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struct VerificClockEdge {
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Verific::Net *clock_net = nullptr;
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SigBit clock_sig = State::Sx;
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bool posedge = false;
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VerificClockEdge(VerificImporter *importer, Verific::Instance *inst);
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};
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struct VerificImporter
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{
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RTLIL::Module *module;
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Verific::Netlist *netlist;
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std::map<Verific::Net*, RTLIL::SigBit> net_map;
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std::map<Verific::Net*, Verific::Net*> sva_posedge_map;
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bool mode_gates, mode_keep, mode_nosva, mode_names;
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VerificImporter(bool mode_gates, bool mode_keep, bool mode_nosva, bool mode_names);
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RTLIL::SigBit net_map_at(Verific::Net *net);
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void import_attributes(dict<RTLIL::IdString, RTLIL::Const> &attributes, Verific::DesignObj *obj);
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RTLIL::SigSpec operatorInput(Verific::Instance *inst);
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RTLIL::SigSpec operatorInput1(Verific::Instance *inst);
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RTLIL::SigSpec operatorInput2(Verific::Instance *inst);
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RTLIL::SigSpec operatorInport(Verific::Instance *inst, const char *portname);
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RTLIL::SigSpec operatorOutput(Verific::Instance *inst);
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bool import_netlist_instance_gates(Verific::Instance *inst, RTLIL::IdString inst_name);
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bool import_netlist_instance_cells(Verific::Instance *inst, RTLIL::IdString inst_name);
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void merge_past_ffs_clock(pool<RTLIL::Cell*> &candidates, SigBit clock, bool clock_pol);
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void merge_past_ffs(pool<RTLIL::Cell*> &candidates);
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void import_netlist(RTLIL::Design *design, Verific::Netlist *nl, std::set<Verific::Netlist*> &nl_todo);
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};
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void import_sva_assert(VerificImporter *importer, Verific::Instance *inst);
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void import_sva_assume(VerificImporter *importer, Verific::Instance *inst);
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void import_sva_cover(VerificImporter *importer, Verific::Instance *inst);
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YOSYS_NAMESPACE_END
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#endif
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