mirror of https://github.com/YosysHQ/yosys.git
389 lines
12 KiB
C++
389 lines
12 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/sigtools.h"
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#include "kernel/log.h"
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#include "kernel/celltypes.h"
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#include <stdlib.h>
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#include <stdio.h>
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#include <set>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct OptReduceWorker
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{
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RTLIL::Design *design;
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RTLIL::Module *module;
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SigMap assign_map;
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int total_count;
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bool did_something;
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void opt_reduce(pool<RTLIL::Cell*> &cells, SigSet<RTLIL::Cell*> &drivers, RTLIL::Cell *cell)
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{
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if (cells.count(cell) == 0)
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return;
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cells.erase(cell);
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RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A));
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pool<RTLIL::SigBit> new_sig_a_bits;
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for (auto &bit : sig_a.to_sigbit_set())
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{
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if (bit == RTLIL::State::S0) {
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if (cell->type == ID($reduce_and)) {
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new_sig_a_bits.clear();
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new_sig_a_bits.insert(RTLIL::State::S0);
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break;
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}
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continue;
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}
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if (bit == RTLIL::State::S1) {
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if (cell->type == ID($reduce_or)) {
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new_sig_a_bits.clear();
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new_sig_a_bits.insert(RTLIL::State::S1);
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break;
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}
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continue;
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}
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if (bit.wire == NULL) {
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new_sig_a_bits.insert(bit);
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continue;
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}
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bool imported_children = false;
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for (auto child_cell : drivers.find(bit)) {
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if (child_cell->type == cell->type) {
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opt_reduce(cells, drivers, child_cell);
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if (child_cell->getPort(ID::Y)[0] == bit) {
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pool<RTLIL::SigBit> child_sig_a_bits = assign_map(child_cell->getPort(ID::A)).to_sigbit_pool();
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new_sig_a_bits.insert(child_sig_a_bits.begin(), child_sig_a_bits.end());
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} else
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new_sig_a_bits.insert(RTLIL::State::S0);
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imported_children = true;
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}
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}
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if (!imported_children)
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new_sig_a_bits.insert(bit);
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}
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RTLIL::SigSpec new_sig_a(new_sig_a_bits);
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if (new_sig_a != sig_a || sig_a.size() != cell->getPort(ID::A).size()) {
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log(" New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a));
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did_something = true;
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total_count++;
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}
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cell->setPort(ID::A, new_sig_a);
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cell->parameters[ID(A_WIDTH)] = RTLIL::Const(new_sig_a.size());
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return;
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}
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void opt_mux(RTLIL::Cell *cell)
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{
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RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A));
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RTLIL::SigSpec sig_b = assign_map(cell->getPort(ID::B));
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RTLIL::SigSpec sig_s = assign_map(cell->getPort(ID(S)));
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RTLIL::SigSpec new_sig_b, new_sig_s;
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pool<RTLIL::SigSpec> handled_sig;
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handled_sig.insert(sig_a);
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for (int i = 0; i < sig_s.size(); i++)
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{
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RTLIL::SigSpec this_b = sig_b.extract(i*sig_a.size(), sig_a.size());
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if (handled_sig.count(this_b) > 0)
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continue;
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RTLIL::SigSpec this_s = sig_s.extract(i, 1);
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for (int j = i+1; j < sig_s.size(); j++) {
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RTLIL::SigSpec that_b = sig_b.extract(j*sig_a.size(), sig_a.size());
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if (this_b == that_b)
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this_s.append(sig_s.extract(j, 1));
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}
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if (this_s.size() > 1)
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{
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RTLIL::Cell *reduce_or_cell = module->addCell(NEW_ID, ID($reduce_or));
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reduce_or_cell->setPort(ID::A, this_s);
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reduce_or_cell->parameters[ID(A_SIGNED)] = RTLIL::Const(0);
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reduce_or_cell->parameters[ID(A_WIDTH)] = RTLIL::Const(this_s.size());
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reduce_or_cell->parameters[ID(Y_WIDTH)] = RTLIL::Const(1);
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RTLIL::Wire *reduce_or_wire = module->addWire(NEW_ID);
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this_s = RTLIL::SigSpec(reduce_or_wire);
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reduce_or_cell->setPort(ID::Y, this_s);
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}
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new_sig_b.append(this_b);
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new_sig_s.append(this_s);
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handled_sig.insert(this_b);
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}
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if (new_sig_s.size() != sig_s.size()) {
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log(" New ctrl vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_s));
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did_something = true;
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total_count++;
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}
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if (new_sig_s.size() == 0)
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{
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module->connect(RTLIL::SigSig(cell->getPort(ID::Y), cell->getPort(ID::A)));
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assign_map.add(cell->getPort(ID::Y), cell->getPort(ID::A));
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module->remove(cell);
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}
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else
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{
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cell->setPort(ID::B, new_sig_b);
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cell->setPort(ID(S), new_sig_s);
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if (new_sig_s.size() > 1) {
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cell->parameters[ID(S_WIDTH)] = RTLIL::Const(new_sig_s.size());
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} else {
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cell->type = ID($mux);
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cell->parameters.erase(ID(S_WIDTH));
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}
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}
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}
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void opt_mux_bits(RTLIL::Cell *cell)
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{
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std::vector<RTLIL::SigBit> sig_a = assign_map(cell->getPort(ID::A)).to_sigbit_vector();
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std::vector<RTLIL::SigBit> sig_b = assign_map(cell->getPort(ID::B)).to_sigbit_vector();
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std::vector<RTLIL::SigBit> sig_y = assign_map(cell->getPort(ID::Y)).to_sigbit_vector();
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std::vector<RTLIL::SigBit> new_sig_y;
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RTLIL::SigSig old_sig_conn;
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std::vector<std::vector<RTLIL::SigBit>> consolidated_in_tuples;
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std::map<std::vector<RTLIL::SigBit>, RTLIL::SigBit> consolidated_in_tuples_map;
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for (int i = 0; i < int(sig_y.size()); i++)
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{
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std::vector<RTLIL::SigBit> in_tuple;
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bool all_tuple_bits_same = true;
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in_tuple.push_back(sig_a.at(i));
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for (int j = i; j < int(sig_b.size()); j += int(sig_a.size())) {
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if (sig_b.at(j) != sig_a.at(i))
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all_tuple_bits_same = false;
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in_tuple.push_back(sig_b.at(j));
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}
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if (all_tuple_bits_same)
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{
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old_sig_conn.first.append_bit(sig_y.at(i));
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old_sig_conn.second.append_bit(sig_a.at(i));
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}
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else if (consolidated_in_tuples_map.count(in_tuple))
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{
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old_sig_conn.first.append_bit(sig_y.at(i));
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old_sig_conn.second.append_bit(consolidated_in_tuples_map.at(in_tuple));
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}
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else
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{
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consolidated_in_tuples_map[in_tuple] = sig_y.at(i);
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consolidated_in_tuples.push_back(in_tuple);
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new_sig_y.push_back(sig_y.at(i));
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}
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}
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if (new_sig_y.size() != sig_y.size())
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{
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log(" Consolidated identical input bits for %s cell %s:\n", cell->type.c_str(), cell->name.c_str());
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log(" Old ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort(ID::A)),
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log_signal(cell->getPort(ID::B)), log_signal(cell->getPort(ID::Y)));
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cell->setPort(ID::A, RTLIL::SigSpec());
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for (auto &in_tuple : consolidated_in_tuples) {
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RTLIL::SigSpec new_a = cell->getPort(ID::A);
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new_a.append(in_tuple.at(0));
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cell->setPort(ID::A, new_a);
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}
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cell->setPort(ID::B, RTLIL::SigSpec());
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for (int i = 1; i <= cell->getPort(ID(S)).size(); i++)
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for (auto &in_tuple : consolidated_in_tuples) {
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RTLIL::SigSpec new_b = cell->getPort(ID::B);
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new_b.append(in_tuple.at(i));
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cell->setPort(ID::B, new_b);
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}
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cell->parameters[ID(WIDTH)] = RTLIL::Const(new_sig_y.size());
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cell->setPort(ID::Y, new_sig_y);
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log(" New ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort(ID::A)),
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log_signal(cell->getPort(ID::B)), log_signal(cell->getPort(ID::Y)));
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log(" New connections: %s = %s\n", log_signal(old_sig_conn.first), log_signal(old_sig_conn.second));
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module->connect(old_sig_conn);
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module->check();
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did_something = true;
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total_count++;
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}
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}
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OptReduceWorker(RTLIL::Design *design, RTLIL::Module *module, bool do_fine) :
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design(design), module(module), assign_map(module)
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{
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log(" Optimizing cells in module %s.\n", module->name.c_str());
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total_count = 0;
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did_something = true;
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SigPool mem_wren_sigs;
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for (auto &cell_it : module->cells_) {
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RTLIL::Cell *cell = cell_it.second;
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if (cell->type == ID($mem))
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mem_wren_sigs.add(assign_map(cell->getPort(ID(WR_EN))));
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if (cell->type == ID($memwr))
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mem_wren_sigs.add(assign_map(cell->getPort(ID(EN))));
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}
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for (auto &cell_it : module->cells_) {
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RTLIL::Cell *cell = cell_it.second;
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if (cell->type == ID($dff) && mem_wren_sigs.check_any(assign_map(cell->getPort(ID(Q)))))
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mem_wren_sigs.add(assign_map(cell->getPort(ID(D))));
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}
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bool keep_expanding_mem_wren_sigs = true;
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while (keep_expanding_mem_wren_sigs) {
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keep_expanding_mem_wren_sigs = false;
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for (auto &cell_it : module->cells_) {
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RTLIL::Cell *cell = cell_it.second;
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if (cell->type == ID($mux) && mem_wren_sigs.check_any(assign_map(cell->getPort(ID::Y)))) {
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if (!mem_wren_sigs.check_all(assign_map(cell->getPort(ID::A))) ||
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!mem_wren_sigs.check_all(assign_map(cell->getPort(ID::B))))
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keep_expanding_mem_wren_sigs = true;
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mem_wren_sigs.add(assign_map(cell->getPort(ID::A)));
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mem_wren_sigs.add(assign_map(cell->getPort(ID::B)));
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}
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}
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}
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while (did_something)
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{
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did_something = false;
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// merge trees of reduce_* cells to one single cell and unify input vectors
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// (only handle reduce_and and reduce_or for various reasons)
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const IdString type_list[] = { ID($reduce_or), ID($reduce_and) };
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for (auto type : type_list)
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{
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SigSet<RTLIL::Cell*> drivers;
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pool<RTLIL::Cell*> cells;
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for (auto &cell_it : module->cells_) {
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RTLIL::Cell *cell = cell_it.second;
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if (cell->type != type || !design->selected(module, cell))
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continue;
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drivers.insert(assign_map(cell->getPort(ID::Y)), cell);
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cells.insert(cell);
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}
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while (cells.size() > 0) {
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RTLIL::Cell *cell = *cells.begin();
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opt_reduce(cells, drivers, cell);
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}
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}
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// merge identical inputs on $mux and $pmux cells
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std::vector<RTLIL::Cell*> cells;
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for (auto &it : module->cells_)
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if ((it.second->type == ID($mux) || it.second->type == ID($pmux)) && design->selected(module, it.second))
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cells.push_back(it.second);
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for (auto cell : cells)
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{
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// this optimization is to aggressive for most coarse-grain applications.
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// but we always want it for multiplexers driving write enable ports.
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if (do_fine || mem_wren_sigs.check_any(assign_map(cell->getPort(ID::Y))))
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opt_mux_bits(cell);
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opt_mux(cell);
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}
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}
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}
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};
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struct OptReducePass : public Pass {
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OptReducePass() : Pass("opt_reduce", "simplify large MUXes and AND/OR gates") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" opt_reduce [options] [selection]\n");
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log("\n");
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log("This pass performs two interlinked optimizations:\n");
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log("\n");
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log("1. it consolidates trees of large AND gates or OR gates and eliminates\n");
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log("duplicated inputs.\n");
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log("\n");
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log("2. it identifies duplicated inputs to MUXes and replaces them with a single\n");
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log("input with the original control signals OR'ed together.\n");
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log("\n");
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log(" -fine\n");
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log(" perform fine-grain optimizations\n");
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log("\n");
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log(" -full\n");
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log(" alias for -fine\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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bool do_fine = false;
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log_header(design, "Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-fine") {
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do_fine = true;
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continue;
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}
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if (args[argidx] == "-full") {
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do_fine = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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int total_count = 0;
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for (auto module : design->selected_modules())
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while (1) {
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OptReduceWorker worker(design, module, do_fine);
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total_count += worker.total_count;
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if (worker.total_count == 0)
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break;
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}
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if (total_count)
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design->scratchpad_set_bool("opt.did_something", true);
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log("Performed a total of %d changes.\n", total_count);
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}
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} OptReducePass;
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PRIVATE_NAMESPACE_END
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