mirror of https://github.com/YosysHQ/yosys.git
432 lines
10 KiB
Verilog
432 lines
10 KiB
Verilog
module LUT1(output O, input I0);
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parameter [1:0] INIT = 0;
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assign O = I0 ? INIT[1] : INIT[0];
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endmodule
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module LUT2(output O, input I0, I1);
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parameter [3:0] INIT = 0;
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wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0];
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assign O = I0 ? s1[1] : s1[0];
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endmodule
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module LUT3(output O, input I0, I1, I2);
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parameter [7:0] INIT = 0;
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wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0];
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wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
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assign O = I0 ? s1[1] : s1[0];
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endmodule
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module LUT4(output O, input I0, I1, I2, I3);
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parameter [15:0] INIT = 0;
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wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
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wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
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wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
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assign O = I0 ? s1[1] : s1[0];
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endmodule
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module LUT4_HA(output O, Co, input I0, I1, I2, I3, Ci);
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parameter [15:0] INIT = 0;
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parameter I0MUX = 1'b1;
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wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0];
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wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0];
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wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0];
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wire I0_sel = I0MUX ? Ci : I0;
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assign O = I0_sel ? s1[1] : s1[0];
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assign Co = (Ci & I1) | (Ci & I2) | (I1 & I2);
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endmodule
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module LUTFF(input CLK, D, output reg O);
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initial O = 1'b0;
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always @ (posedge CLK) begin
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O <= D;
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end
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endmodule
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module FABULOUS_MUX2(input I0, I1, S0, output O);
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assign O = S0 ? I1 : I0;
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endmodule
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module FABULOUS_MUX4(input I0, I1, I2, I3, S0, S1, output O);
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wire A0 = S0 ? I1 : I0;
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wire A1 = S0 ? I3 : I2;
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assign O = S1 ? A1 : A0;
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endmodule
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module FABULOUS_MUX8(input I0, I1, I2, I3, I4, I5, I6, I7, S0, S1, S2, output O);
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wire A0 = S0 ? I1 : I0;
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wire A1 = S0 ? I3 : I2;
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wire A2 = S0 ? I5 : I4;
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wire A3 = S0 ? I7 : I6;
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wire B0 = S1 ? A1 : A0;
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wire B1 = S1 ? A3 : A2;
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assign O = S2 ? B1 : B0;
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endmodule
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module FABULOUS_LC #(
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parameter K = 4,
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parameter [2**K-1:0] INIT = 0,
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parameter DFF_ENABLE = 1'b0
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) (
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input CLK,
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input [K-1:0] I,
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output O,
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output Q
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);
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wire f_wire;
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//LUT #(.K(K), .INIT(INIT)) lut_i(.I(I), .Q(f_wire));
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generate
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if (K == 1) begin
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LUT1 #(.INIT(INIT)) lut1 (.O(f_wire), .I0(I[0]));
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end else
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if (K == 2) begin
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LUT2 #(.INIT(INIT)) lut2 (.O(f_wire), .I0(I[0]), .I1(I[1]));
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end else
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if (K == 3) begin
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LUT3 #(.INIT(INIT)) lut3 (.O(f_wire), .I0(I[0]), .I1(I[1]), .I2(I[2]));
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end else
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if (K == 4) begin
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LUT4 #(.INIT(INIT)) lut4 (.O(f_wire), .I0(I[0]), .I1(I[1]), .I2(I[2]), .I3(I[3]));
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end
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endgenerate
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LUTFF dff_i(.CLK(CLK), .D(f_wire), .Q(Q));
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assign O = f_wire;
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endmodule
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(* blackbox *)
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module Global_Clock (output CLK);
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`ifndef SYNTHESIS
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initial CLK = 0;
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always #10 CLK = ~CLK;
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`endif
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endmodule
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(* blackbox, keep *)
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module InPass4_frame_config (input CLK, output O0, O1, O2, O3);
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endmodule
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(* blackbox, keep *)
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module OutPass4_frame_config (input CLK, I0, I1, I2, I3);
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endmodule
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(* keep *)
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module IO_1_bidirectional_frame_config_pass (input CLK, T, I, output Q, O, (* iopad_external_pin *) inout PAD);
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assign PAD = T ? 1'bz : I;
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assign O = PAD;
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reg Q_q;
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always @(posedge CLK) Q_q <= O;
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assign Q = Q_q;
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endmodule
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module MULADD (A7, A6, A5, A4, A3, A2, A1, A0, B7, B6, B5, B4, B3, B2, B1, B0, C19, C18, C17, C16, C15, C14, C13, C12, C11, C10, C9, C8, C7, C6, C5, C4, C3, C2, C1, C0, Q19, Q18, Q17, Q16, Q15, Q14, Q13, Q12, Q11, Q10, Q9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0, clr, CLK);
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parameter A_reg = 1'b0;
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parameter B_reg = 1'b0;
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parameter C_reg = 1'b0;
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parameter ACC = 1'b0;
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parameter signExtension = 1'b0;
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parameter ACCout = 1'b0;
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//parameter NoConfigBits = 6;// has to be adjusted manually (we don't use an arithmetic parser for the value)
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// IMPORTANT: this has to be in a dedicated line
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input A7;// operand A
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input A6;
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input A5;
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input A4;
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input A3;
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input A2;
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input A1;
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input A0;
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input B7;// operand B
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input B6;
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input B5;
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input B4;
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input B3;
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input B2;
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input B1;
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input B0;
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input C19;// operand C
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input C18;
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input C17;
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input C16;
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input C15;
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input C14;
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input C13;
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input C12;
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input C11;
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input C10;
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input C9;
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input C8;
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input C7;
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input C6;
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input C5;
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input C4;
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input C3;
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input C2;
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input C1;
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input C0;
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output Q19;// result
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output Q18;
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output Q17;
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output Q16;
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output Q15;
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output Q14;
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output Q13;
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output Q12;
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output Q11;
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output Q10;
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output Q9;
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output Q8;
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output Q7;
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output Q6;
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output Q5;
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output Q4;
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output Q3;
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output Q2;
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output Q1;
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output Q0;
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input clr;
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input CLK; // EXTERNAL // SHARED_PORT // ## the EXTERNAL keyword will send this sisgnal all the way to top and the //SHARED Allows multiple BELs using the same port (e.g. for exporting a clock to the top)
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// GLOBAL all primitive pins that are connected to the switch matrix have to go before the GLOBAL label
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wire [7:0] A; // port A read data
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wire [7:0] B; // port B read data
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wire [19:0] C; // port B read data
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reg [7:0] A_q; // port A read data register
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reg [7:0] B_q; // port B read data register
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reg [19:0] C_q; // port B read data register
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wire [7:0] OPA; // port A
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wire [7:0] OPB; // port B
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wire [19:0] OPC; // port B
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reg [19:0] ACC_data ; // accumulator register
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wire [19:0] sum;// port B read data register
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wire [19:0] sum_in;// port B read data register
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wire [15:0] product;
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wire [19:0] product_extended;
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assign A = {A7,A6,A5,A4,A3,A2,A1,A0};
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assign B = {B7,B6,B5,B4,B3,B2,B1,B0};
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assign C = {C19,C18,C17,C16,C15,C14,C13,C12,C11,C10,C9,C8,C7,C6,C5,C4,C3,C2,C1,C0};
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assign OPA = A_reg ? A_q : A;
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assign OPB = B_reg ? B_q : B;
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assign OPC = C_reg ? C_q : C;
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assign sum_in = ACC ? ACC_data : OPC;// we can
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assign product = OPA * OPB;
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// The sign extension was not tested
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assign product_extended = signExtension ? {product[15],product[15],product[15],product[15],product} : {4'b0000,product};
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assign sum = product_extended + sum_in;
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assign Q19 = ACCout ? ACC_data[19] : sum[19];
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assign Q18 = ACCout ? ACC_data[18] : sum[18];
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assign Q17 = ACCout ? ACC_data[17] : sum[17];
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assign Q16 = ACCout ? ACC_data[16] : sum[16];
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assign Q15 = ACCout ? ACC_data[15] : sum[15];
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assign Q14 = ACCout ? ACC_data[14] : sum[14];
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assign Q13 = ACCout ? ACC_data[13] : sum[13];
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assign Q12 = ACCout ? ACC_data[12] : sum[12];
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assign Q11 = ACCout ? ACC_data[11] : sum[11];
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assign Q10 = ACCout ? ACC_data[10] : sum[10];
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assign Q9 = ACCout ? ACC_data[9] : sum[9];
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assign Q8 = ACCout ? ACC_data[8] : sum[8];
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assign Q7 = ACCout ? ACC_data[7] : sum[7];
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assign Q6 = ACCout ? ACC_data[6] : sum[6];
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assign Q5 = ACCout ? ACC_data[5] : sum[5];
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assign Q4 = ACCout ? ACC_data[4] : sum[4];
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assign Q3 = ACCout ? ACC_data[3] : sum[3];
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assign Q2 = ACCout ? ACC_data[2] : sum[2];
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assign Q1 = ACCout ? ACC_data[1] : sum[1];
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assign Q0 = ACCout ? ACC_data[0] : sum[0];
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always @ (posedge CLK)
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begin
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A_q <= A;
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B_q <= B;
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C_q <= C;
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if (clr == 1'b1) begin
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ACC_data <= 20'b00000000000000000000;
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end else begin
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ACC_data <= sum;
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end
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end
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endmodule
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module RegFile_32x4 (D0, D1, D2, D3, W_ADR0, W_ADR1, W_ADR2, W_ADR3, W_ADR4, W_en, AD0, AD1, AD2, AD3, A_ADR0, A_ADR1, A_ADR2, A_ADR3, A_ADR4, BD0, BD1, BD2, BD3, B_ADR0, B_ADR1, B_ADR2, B_ADR3, B_ADR4, CLK);
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//parameter NoConfigBits = 2;// has to be adjusted manually (we don't use an arithmetic parser for the value)
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parameter AD_reg = 1'b0;
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parameter BD_reg = 1'b0;
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// IMPORTANT: this has to be in a dedicated line
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input D0; // Register File write port
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input D1;
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input D2;
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input D3;
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input W_ADR0;
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input W_ADR1;
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input W_ADR2;
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input W_ADR3;
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input W_ADR4;
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input W_en;
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output AD0;// Register File read port A
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output AD1;
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output AD2;
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output AD3;
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input A_ADR0;
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input A_ADR1;
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input A_ADR2;
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input A_ADR3;
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input A_ADR4;
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output BD0;//Register File read port B
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output BD1;
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output BD2;
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output BD3;
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input B_ADR0;
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input B_ADR1;
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input B_ADR2;
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input B_ADR3;
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input B_ADR4;
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input CLK;// EXTERNAL // SHARED_PORT // ## the EXTERNAL keyword will send this sisgnal all the way to top and the //SHARED Allows multiple BELs using the same port (e.g. for exporting a clock to the top)
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// GLOBAL all primitive pins that are connected to the switch matrix have to go before the GLOBAL label
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//type memtype is array (31 downto 0) of std_logic_vector(3 downto 0); // 32 entries of 4 bit
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//signal mem : memtype := (others => (others => '0'));
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reg [3:0] mem [31:0];
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wire [4:0] W_ADR;// write address
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wire [4:0] A_ADR;// port A read address
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wire [4:0] B_ADR;// port B read address
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wire [3:0] D; // write data
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wire [3:0] AD; // port A read data
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wire [3:0] BD; // port B read data
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reg [3:0] AD_q; // port A read data register
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reg [3:0] BD_q; // port B read data register
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integer i;
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assign W_ADR = {W_ADR4,W_ADR3,W_ADR2,W_ADR1,W_ADR0};
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assign A_ADR = {A_ADR4,A_ADR3,A_ADR2,A_ADR1,A_ADR0};
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assign B_ADR = {B_ADR4,B_ADR3,B_ADR2,B_ADR1,B_ADR0};
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assign D = {D3,D2,D1,D0};
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initial begin
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for (i=0; i<32; i=i+1) begin
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mem[i] = 4'b0000;
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end
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end
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always @ (posedge CLK) begin : P_write
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if (W_en == 1'b1) begin
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mem[W_ADR] <= D ;
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end
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end
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assign AD = mem[A_ADR];
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assign BD = mem[B_ADR];
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always @ (posedge CLK) begin
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AD_q <= AD;
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BD_q <= BD;
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end
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assign AD0 = AD_reg ? AD_q[0] : AD[0];
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assign AD1 = AD_reg ? AD_q[1] : AD[1];
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assign AD2 = AD_reg ? AD_q[2] : AD[2];
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assign AD3 = AD_reg ? AD_q[3] : AD[3];
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assign BD0 = BD_reg ? BD_q[0] : BD[0];
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assign BD1 = BD_reg ? BD_q[1] : BD[1];
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assign BD2 = BD_reg ? BD_q[2] : BD[2];
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assign BD3 = BD_reg ? BD_q[3] : BD[3];
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endmodule
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`ifdef EQUIV
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`define COMPLEX_DFF
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`endif
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`ifdef COMPLEX_DFF
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module LUTFF_E (
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output reg O,
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input CLK, E, D
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);
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initial O = 1'b0;
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always @(posedge CLK)
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if (E)
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O <= D;
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endmodule
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module LUTFF_SR (
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output reg O,
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input CLK, R, D
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);
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initial O = 1'b0;
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always @(posedge CLK)
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if (R)
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O <= 0;
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else
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O <= D;
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endmodule
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module LUTFF_SS (
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output reg O,
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input CLK, S, D
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);
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initial O = 1'b0;
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always @(posedge CLK)
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if (S)
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O <= 1;
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else
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O <= D;
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endmodule
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module LUTFF_ESR (
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output reg O,
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input CLK, E, R, D
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);
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initial O = 1'b0;
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always @(posedge CLK)
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if (E) begin
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if (R)
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O <= 0;
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else
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O <= D;
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end
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endmodule
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module LUTFF_ESS (
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output reg O,
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input CLK, E, S, D
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);
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initial O = 1'b0;
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always @(posedge CLK)
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if (E) begin
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if (S)
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O <= 1;
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else
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O <= D;
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end
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endmodule
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`endif // COMPLEX_DFF
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