mirror of https://github.com/YosysHQ/yosys.git
342 lines
10 KiB
C++
342 lines
10 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/sigtools.h"
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#include "kernel/log.h"
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#include "kernel/celltypes.h"
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#include "libs/sha1/sha1.h"
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#include <stdlib.h>
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#include <stdio.h>
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#include <set>
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#define USE_CELL_HASH_CACHE
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct OptShareWorker
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{
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RTLIL::Design *design;
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RTLIL::Module *module;
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SigMap assign_map;
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SigMap dff_init_map;
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bool mode_share_all;
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CellTypes ct;
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int total_count;
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#ifdef USE_CELL_HASH_CACHE
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dict<const RTLIL::Cell*, std::string> cell_hash_cache;
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#endif
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#ifdef USE_CELL_HASH_CACHE
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std::string int_to_hash_string(unsigned int v)
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{
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if (v == 0)
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return "0";
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std::string str = "";
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while (v > 0) {
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str += 'a' + (v & 15);
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v = v >> 4;
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}
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return str;
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}
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std::string hash_cell_parameters_and_connections(const RTLIL::Cell *cell)
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{
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if (cell_hash_cache.count(cell) > 0)
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return cell_hash_cache[cell];
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std::string hash_string = cell->type.str() + "\n";
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for (auto &it : cell->parameters)
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hash_string += "P " + it.first.str() + "=" + it.second.as_string() + "\n";
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const dict<RTLIL::IdString, RTLIL::SigSpec> *conn = &cell->connections();
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dict<RTLIL::IdString, RTLIL::SigSpec> alt_conn;
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if (cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" || cell->type == "$xnor" || cell->type == "$add" || cell->type == "$mul" ||
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cell->type == "$logic_and" || cell->type == "$logic_or" || cell->type == "$_AND_" || cell->type == "$_OR_" || cell->type == "$_XOR_") {
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alt_conn = *conn;
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if (assign_map(alt_conn.at("\\A")) < assign_map(alt_conn.at("\\B"))) {
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alt_conn["\\A"] = conn->at("\\B");
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alt_conn["\\B"] = conn->at("\\A");
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}
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conn = &alt_conn;
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} else
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if (cell->type == "$reduce_xor" || cell->type == "$reduce_xnor") {
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alt_conn = *conn;
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assign_map.apply(alt_conn.at("\\A"));
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alt_conn.at("\\A").sort();
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conn = &alt_conn;
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} else
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if (cell->type == "$reduce_and" || cell->type == "$reduce_or" || cell->type == "$reduce_bool") {
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alt_conn = *conn;
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assign_map.apply(alt_conn.at("\\A"));
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alt_conn.at("\\A").sort_and_unify();
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conn = &alt_conn;
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}
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for (auto &it : *conn) {
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if (cell->output(it.first))
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continue;
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RTLIL::SigSpec sig = it.second;
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assign_map.apply(sig);
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hash_string += "C " + it.first.str() + "=";
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for (auto &chunk : sig.chunks()) {
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if (chunk.wire)
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hash_string += "{" + chunk.wire->name.str() + " " +
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int_to_hash_string(chunk.offset) + " " +
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int_to_hash_string(chunk.width) + "}";
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else
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hash_string += RTLIL::Const(chunk.data).as_string();
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}
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hash_string += "\n";
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}
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cell_hash_cache[cell] = sha1(hash_string);
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return cell_hash_cache[cell];
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}
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#endif
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bool compare_cell_parameters_and_connections(const RTLIL::Cell *cell1, const RTLIL::Cell *cell2, bool <)
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{
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#ifdef USE_CELL_HASH_CACHE
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std::string hash1 = hash_cell_parameters_and_connections(cell1);
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std::string hash2 = hash_cell_parameters_and_connections(cell2);
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if (hash1 != hash2) {
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lt = hash1 < hash2;
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return true;
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}
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#endif
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if (cell1->parameters != cell2->parameters) {
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std::map<RTLIL::IdString, RTLIL::Const> p1(cell1->parameters.begin(), cell1->parameters.end());
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std::map<RTLIL::IdString, RTLIL::Const> p2(cell2->parameters.begin(), cell2->parameters.end());
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lt = p1 < p2;
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return true;
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}
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dict<RTLIL::IdString, RTLIL::SigSpec> conn1 = cell1->connections();
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dict<RTLIL::IdString, RTLIL::SigSpec> conn2 = cell2->connections();
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for (auto &it : conn1) {
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if (cell1->output(it.first))
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it.second = RTLIL::SigSpec();
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else
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assign_map.apply(it.second);
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}
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for (auto &it : conn2) {
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if (cell2->output(it.first))
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it.second = RTLIL::SigSpec();
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else
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assign_map.apply(it.second);
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}
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if (cell1->type == "$and" || cell1->type == "$or" || cell1->type == "$xor" || cell1->type == "$xnor" || cell1->type == "$add" || cell1->type == "$mul" ||
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cell1->type == "$logic_and" || cell1->type == "$logic_or" || cell1->type == "$_AND_" || cell1->type == "$_OR_" || cell1->type == "$_XOR_") {
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if (conn1.at("\\A") < conn1.at("\\B")) {
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RTLIL::SigSpec tmp = conn1["\\A"];
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conn1["\\A"] = conn1["\\B"];
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conn1["\\B"] = tmp;
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}
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if (conn2.at("\\A") < conn2.at("\\B")) {
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RTLIL::SigSpec tmp = conn2["\\A"];
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conn2["\\A"] = conn2["\\B"];
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conn2["\\B"] = tmp;
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}
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} else
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if (cell1->type == "$reduce_xor" || cell1->type == "$reduce_xnor") {
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conn1["\\A"].sort();
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conn2["\\A"].sort();
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} else
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if (cell1->type == "$reduce_and" || cell1->type == "$reduce_or" || cell1->type == "$reduce_bool") {
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conn1["\\A"].sort_and_unify();
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conn2["\\A"].sort_and_unify();
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}
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if (conn1 != conn2) {
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std::map<RTLIL::IdString, RTLIL::SigSpec> c1(conn1.begin(), conn1.end());
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std::map<RTLIL::IdString, RTLIL::SigSpec> c2(conn2.begin(), conn2.end());
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lt = c1 < c2;
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return true;
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}
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if (cell1->type.substr(0, 1) == "$" && conn1.count("\\Q") != 0) {
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std::vector<RTLIL::SigBit> q1 = dff_init_map(cell1->getPort("\\Q")).to_sigbit_vector();
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std::vector<RTLIL::SigBit> q2 = dff_init_map(cell2->getPort("\\Q")).to_sigbit_vector();
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for (size_t i = 0; i < q1.size(); i++)
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if ((q1.at(i).wire == NULL || q2.at(i).wire == NULL) && q1.at(i) != q2.at(i)) {
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lt = q1.at(i) < q2.at(i);
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return true;
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}
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}
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return false;
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}
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bool compare_cells(const RTLIL::Cell *cell1, const RTLIL::Cell *cell2)
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{
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if (cell1->type != cell2->type)
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return cell1->type < cell2->type;
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if ((!mode_share_all && !ct.cell_known(cell1->type)) || !cell1->known())
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return cell1 < cell2;
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if (cell1->has_keep_attr() || cell2->has_keep_attr())
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return cell1 < cell2;
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bool lt;
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if (compare_cell_parameters_and_connections(cell1, cell2, lt))
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return lt;
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return false;
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}
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struct CompareCells {
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OptShareWorker *that;
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CompareCells(OptShareWorker *that) : that(that) {}
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bool operator()(const RTLIL::Cell *cell1, const RTLIL::Cell *cell2) const {
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return that->compare_cells(cell1, cell2);
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}
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};
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OptShareWorker(RTLIL::Design *design, RTLIL::Module *module, bool mode_nomux, bool mode_share_all) :
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design(design), module(module), assign_map(module), mode_share_all(mode_share_all)
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{
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total_count = 0;
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ct.setup_internals();
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ct.setup_internals_mem();
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ct.setup_stdcells();
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ct.setup_stdcells_mem();
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if (mode_nomux) {
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ct.cell_types.erase("$mux");
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ct.cell_types.erase("$pmux");
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}
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log("Finding identical cells in module `%s'.\n", module->name.c_str());
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assign_map.set(module);
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dff_init_map.set(module);
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for (auto &it : module->wires_)
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if (it.second->attributes.count("\\init") != 0)
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dff_init_map.add(it.second, it.second->attributes.at("\\init"));
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bool did_something = true;
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while (did_something)
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{
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#ifdef USE_CELL_HASH_CACHE
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cell_hash_cache.clear();
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#endif
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std::vector<RTLIL::Cell*> cells;
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cells.reserve(module->cells_.size());
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for (auto &it : module->cells_) {
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if (!design->selected(module, it.second))
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continue;
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if (ct.cell_known(it.second->type) || (mode_share_all && it.second->known()))
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cells.push_back(it.second);
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}
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did_something = false;
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std::map<RTLIL::Cell*, RTLIL::Cell*, CompareCells> sharemap(CompareCells(this));
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for (auto cell : cells)
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{
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if (sharemap.count(cell) > 0) {
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did_something = true;
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log(" Cell `%s' is identical to cell `%s'.\n", cell->name.c_str(), sharemap[cell]->name.c_str());
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for (auto &it : cell->connections()) {
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if (cell->output(it.first)) {
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RTLIL::SigSpec other_sig = sharemap[cell]->getPort(it.first);
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log(" Redirecting output %s: %s = %s\n", it.first.c_str(),
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log_signal(it.second), log_signal(other_sig));
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module->connect(RTLIL::SigSig(it.second, other_sig));
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assign_map.add(it.second, other_sig);
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}
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}
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log(" Removing %s cell `%s' from module `%s'.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str());
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#ifdef USE_CELL_HASH_CACHE
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cell_hash_cache.erase(cell);
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#endif
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module->remove(cell);
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total_count++;
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} else {
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sharemap[cell] = cell;
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}
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}
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}
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}
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};
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struct OptSharePass : public Pass {
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OptSharePass() : Pass("opt_share", "consolidate identical cells") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" opt_share [options] [selection]\n");
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log("\n");
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log("This pass identifies cells with identical type and input signals. Such cells\n");
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log("are then merged to one cell.\n");
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log("\n");
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log(" -nomux\n");
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log(" Do not merge MUX cells.\n");
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log("\n");
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log(" -share_all\n");
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log(" Operate on all cell types, not just built-in types.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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log_header("Executing OPT_SHARE pass (detect identical cells).\n");
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bool mode_nomux = false;
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bool mode_share_all = false;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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std::string arg = args[argidx];
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if (arg == "-nomux") {
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mode_nomux = true;
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continue;
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}
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if (arg == "-share_all") {
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mode_share_all = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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int total_count = 0;
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for (auto module : design->selected_modules()) {
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OptShareWorker worker(design, module, mode_nomux, mode_share_all);
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total_count += worker.total_count;
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}
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if (total_count)
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design->scratchpad_set_bool("opt.did_something", true);
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log("Removed a total of %d cells.\n", total_count);
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}
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} OptSharePass;
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PRIVATE_NAMESPACE_END
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