mirror of https://github.com/YosysHQ/yosys.git
79 lines
2.6 KiB
C++
79 lines
2.6 KiB
C++
#include "kernel/rtlil.h"
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#include "kernel/register.h"
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#include "kernel/log.h"
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#include "kernel/sigtools.h"
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struct MyPass : public Pass {
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MyPass() : Pass("my_cmd", "just a simple test") { }
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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log("Arguments to my_cmd:\n");
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for (auto &arg : args)
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log(" %s\n", arg.c_str());
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log("Modules in current design:\n");
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for (auto &mod : design->modules)
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log(" %s (%zd wires, %zd cells)\n", RTLIL::id2cstr(mod.first),
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mod.second->wires_.size(), mod.second->cells_.size());
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}
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} MyPass;
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struct Test1Pass : public Pass {
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Test1Pass() : Pass("test1", "creating the absval module") { }
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virtual void execute(std::vector<std::string>, RTLIL::Design *design)
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{
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RTLIL::Module *module = new RTLIL::Module;
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module->name = "\\absval";
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RTLIL::Wire *a = module->new_wire(4, "\\a");
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a->port_input = true;
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a->port_id = 1;
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RTLIL::Wire *y = module->new_wire(4, "\\y");
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y->port_output = true;
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y->port_id = 2;
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RTLIL::Wire *a_inv = module->new_wire(4, NEW_ID);
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module->addNeg(NEW_ID, a, a_inv, true);
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module->addMux(NEW_ID, a, a_inv, RTLIL::SigSpec(a, 1, 3), y);
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log("Name of this module: %s\n", RTLIL::id2cstr(module->name));
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if (design->modules.count(module->name) != 0)
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log_error("A module with the name %s already exists!\n",
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RTLIL::id2cstr(module->name));
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design->modules[module->name] = module;
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}
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} Test1Pass;
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struct Test2Pass : public Pass {
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Test2Pass() : Pass("test2", "demonstrating sigmap on test module") { }
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virtual void execute(std::vector<std::string>, RTLIL::Design *design)
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{
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if (design->selection_stack.back().empty())
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log_cmd_error("This command can't operator on an empty selection!\n");
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RTLIL::Module *module = design->modules.at("\\test");
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RTLIL::SigSpec a(module->wires_.at("\\a")), x(module->wires_.at("\\x")),
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y(module->wires_.at("\\y"));
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log("%d %d %d\n", a == x, x == y, y == a); // will print "0 0 0"
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SigMap sigmap(module);
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log("%d %d %d\n", sigmap(a) == sigmap(x), sigmap(x) == sigmap(y),
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sigmap(y) == sigmap(a)); // will print "1 1 1"
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log("Mapped signal x: %s\n", log_signal(sigmap(x)));
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log_header("Doing important stuff!\n");
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log_push();
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for (int i = 0; i < 10; i++)
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log("Log message #%d.\n", i);
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log_pop();
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}
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} Test2Pass;
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