mirror of https://github.com/YosysHQ/yosys.git
28 lines
820 B
Verilog
28 lines
820 B
Verilog
// ---------------------------------------
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// Attach a (combinatorial) black-box onto the output
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// of this LUTRAM primitive to capture its
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// asynchronous read behaviour
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module TRELLIS_DPR16X4 (
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(* techmap_autopurge *) input [3:0] DI,
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(* techmap_autopurge *) input [3:0] WAD,
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(* techmap_autopurge *) input WRE,
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(* techmap_autopurge *) input WCK,
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(* techmap_autopurge *) input [3:0] RAD,
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output [3:0] DO
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);
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parameter WCKMUX = "WCK";
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parameter WREMUX = "WRE";
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parameter [63:0] INITVAL = 64'h0000000000000000;
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wire [3:0] $DO;
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TRELLIS_DPR16X4 #(
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.WCKMUX(WCKMUX), .WREMUX(WREMUX), .INITVAL(INITVAL)
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) _TECHMAP_REPLACE_ (
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.DI(DI), .WAD(WAD), .WRE(WRE), .WCK(WCK),
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.RAD(RAD), .DO($DO)
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);
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$__ABC9_DPR16X4_COMB do (.$DO($DO), .RAD(RAD), .DO(DO));
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endmodule
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