mirror of https://github.com/YosysHQ/yosys.git
150 lines
3.4 KiB
Verilog
150 lines
3.4 KiB
Verilog
module $__XILINX_BLOCKRAM_TDP_ (...);
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parameter INIT = 0;
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parameter OPTION_MODE = "FULL";
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parameter PORT_A_RD_WIDTH = 1;
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parameter PORT_A_WR_WIDTH = 1;
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parameter PORT_A_WR_EN_WIDTH = 1;
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parameter PORT_A_RD_USED = 1;
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parameter PORT_A_WR_USED = 1;
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parameter PORT_A_OPTION_WRITE_MODE = "NO_CHANGE";
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parameter PORT_A_RD_INIT_VALUE = 0;
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parameter PORT_A_RD_SRST_VALUE = 0;
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parameter PORT_B_RD_WIDTH = 1;
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parameter PORT_B_WR_WIDTH = 1;
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parameter PORT_B_WR_EN_WIDTH = 1;
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parameter PORT_B_RD_USED = 0;
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parameter PORT_B_WR_USED = 0;
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parameter PORT_B_OPTION_WRITE_MODE = "NO_CHANGE";
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parameter PORT_B_RD_INIT_VALUE = 0;
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parameter PORT_B_RD_SRST_VALUE = 0;
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input PORT_A_CLK;
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input PORT_A_CLK_EN;
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input [14:0] PORT_A_ADDR;
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input [PORT_A_WR_WIDTH-1:0] PORT_A_WR_DATA;
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input [PORT_A_WR_EN_WIDTH-1:0] PORT_A_WR_EN;
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output [PORT_A_RD_WIDTH-1:0] PORT_A_RD_DATA;
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input PORT_A_RD_SRST;
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input PORT_B_CLK;
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input PORT_B_CLK_EN;
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input [14:0] PORT_B_ADDR;
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input [PORT_B_WR_WIDTH-1:0] PORT_B_WR_DATA;
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input [PORT_B_WR_EN_WIDTH-1:0] PORT_B_WR_EN;
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output [PORT_B_RD_WIDTH-1:0] PORT_B_RD_DATA;
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input PORT_B_RD_SRST;
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`include "brams_defs.vh"
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`define PARAMS_COMMON \
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.WRITE_MODE_A(PORT_A_OPTION_WRITE_MODE), \
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.WRITE_MODE_B(PORT_B_OPTION_WRITE_MODE), \
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.READ_WIDTH_A(PORT_A_RD_USED ? PORT_A_RD_WIDTH : 0), \
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.READ_WIDTH_B(PORT_B_RD_USED ? PORT_B_RD_WIDTH : 0), \
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.WRITE_WIDTH_A(PORT_A_WR_USED ? PORT_A_WR_WIDTH : 0), \
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.WRITE_WIDTH_B(PORT_B_WR_USED ? PORT_B_WR_WIDTH : 0), \
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.DOA_REG(0), \
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.DOB_REG(0), \
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.INIT_A(ival(PORT_A_RD_WIDTH, PORT_A_RD_INIT_VALUE)), \
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.INIT_B(ival(PORT_B_RD_WIDTH, PORT_B_RD_INIT_VALUE)), \
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.SRVAL_A(ival(PORT_A_RD_WIDTH, PORT_A_RD_SRST_VALUE)), \
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.SRVAL_B(ival(PORT_B_RD_WIDTH, PORT_B_RD_SRST_VALUE)),
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`MAKE_DI(DI_A, DIP_A, PORT_A_WR_DATA)
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`MAKE_DI(DI_B, DIP_B, PORT_B_WR_DATA)
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`MAKE_DO(DO_A, DOP_A, PORT_A_RD_DATA)
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`MAKE_DO(DO_B, DOP_B, PORT_B_RD_DATA)
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wire [3:0] WE_A = {4{PORT_A_WR_EN}};
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wire [3:0] WE_B = {4{PORT_B_WR_EN}};
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generate
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if (OPTION_MODE == "FULL") begin
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RAMB16 #(
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`PARAMS_INIT_18
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`PARAMS_INITP_18
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`PARAMS_COMMON
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.RAM_EXTENSION_A("NONE"),
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.RAM_EXTENSION_B("NONE"),
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) _TECHMAP_REPLACE_ (
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.DOA(DO_A),
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.DOPA(DOP_A),
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.DIA(DI_A),
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.DIPA(DIP_A),
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.DOB(DO_B),
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.DOPB(DOP_B),
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.DIB(DI_B),
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.DIPB(DIP_B),
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.ADDRA({1'b1, PORT_A_ADDR[13:0]}),
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.ADDRB({1'b1, PORT_B_ADDR[13:0]}),
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.CLKA(PORT_A_CLK),
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.CLKB(PORT_B_CLK),
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.ENA(PORT_A_CLK_EN),
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.ENB(PORT_B_CLK_EN),
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.REGCEA(1'b0),
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.REGCEB(1'b0),
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.SSRA(PORT_A_RD_SRST),
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.SSRB(PORT_B_RD_SRST),
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.WEA(WE_A),
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.WEB(WE_B),
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);
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end else begin
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wire CAS_A, CAS_B;
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RAMB16 #(
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`PARAMS_INIT_18
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`PARAMS_COMMON
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.RAM_EXTENSION_A("LOWER"),
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.RAM_EXTENSION_B("LOWER"),
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) lower (
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.DIA(DI_A),
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.DIB(DI_B),
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.ADDRA(PORT_A_ADDR),
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.ADDRB(PORT_B_ADDR),
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.CLKA(PORT_A_CLK),
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.CLKB(PORT_B_CLK),
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.ENA(PORT_A_CLK_EN),
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.ENB(PORT_B_CLK_EN),
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.REGCEA(1'b0),
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.REGCEB(1'b0),
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.SSRA(PORT_A_RD_SRST),
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.SSRB(PORT_B_RD_SRST),
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.WEA(WE_A),
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.WEB(WE_B),
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.CASCADEOUTA(CAS_A),
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.CASCADEOUTB(CAS_B),
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);
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RAMB16 #(
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`PARAMS_INIT_18_U
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`PARAMS_COMMON
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.RAM_EXTENSION_A("UPPER"),
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.RAM_EXTENSION_B("UPPER"),
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) upper (
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.DOA(DO_A),
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.DIA(DI_A),
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.DOB(DO_B),
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.DIB(DI_B),
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.ADDRA(PORT_A_ADDR),
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.ADDRB(PORT_B_ADDR),
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.CLKA(PORT_A_CLK),
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.CLKB(PORT_B_CLK),
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.ENA(PORT_A_CLK_EN),
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.ENB(PORT_B_CLK_EN),
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.REGCEA(1'b0),
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.REGCEB(1'b0),
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.SSRA(PORT_A_RD_SRST),
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.SSRB(PORT_B_RD_SRST),
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.WEA(WE_A),
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.WEB(WE_B),
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.CASCADEINA(CAS_A),
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.CASCADEINB(CAS_B),
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);
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end
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endgenerate
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endmodule
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