mirror of https://github.com/YosysHQ/yosys.git
51 lines
1.0 KiB
Plaintext
51 lines
1.0 KiB
Plaintext
read_verilog << EOT
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module top(...);
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input clk;
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input d;
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input sr;
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output reg q0, q1, q2, q3, q4, q5;
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initial q0 = 1'b0;
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initial q1 = 1'b0;
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initial q2 = 1'b1;
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initial q3 = 1'b1;
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initial q4 = 1'bx;
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initial q5 = 1'bx;
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always @(posedge clk) begin
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q0 <= sr ? 1'b0 : d;
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q1 <= sr ? 1'b1 : d;
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q2 <= sr ? 1'b0 : d;
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q3 <= sr ? 1'b1 : d;
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q4 <= sr ? 1'b0 : d;
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q5 <= sr ? 1'b1 : d;
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end
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endmodule
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EOT
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proc
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simplemap
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design -save ref
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dff2dffs
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clean
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select -assert-count 1 w:q0 %x t:$_SDFF_PP0_ %i
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select -assert-count 1 w:q1 %x t:$_SDFF_PP1_ %i
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select -assert-count 1 w:q2 %x t:$_SDFF_PP0_ %i
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select -assert-count 1 w:q3 %x t:$_SDFF_PP1_ %i
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select -assert-count 1 w:q4 %x t:$_SDFF_PP0_ %i
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select -assert-count 1 w:q5 %x t:$_SDFF_PP1_ %i
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design -load ref
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dff2dffs -match-init
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clean
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select -assert-count 1 w:q0 %x t:$_SDFF_PP0_ %i
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select -assert-count 0 w:q1 %x t:$_SDFF_PP1_ %i
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select -assert-count 0 w:q2 %x t:$_SDFF_PP0_ %i
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select -assert-count 1 w:q3 %x t:$_SDFF_PP1_ %i
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select -assert-count 1 w:q4 %x t:$_SDFF_PP0_ %i
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select -assert-count 1 w:q5 %x t:$_SDFF_PP1_ %i
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