yosys/passes
Clifford Wolf 2a9c68e2d6
Merge pull request #1026 from YosysHQ/clifford/fix1023
Keep zero-width wires in opt_clean if and only if they are ports
2019-05-27 13:24:19 +02:00
..
cmds Do not leak file descriptors in cover.cc 2019-05-15 13:51:02 +02:00
equiv Add -undef option to equiv_opt, passed to equiv_induct 2019-04-26 11:16:48 -07:00
fsm fsm_opt: Fix runtime error for FSMs without a reset state 2019-02-07 10:35:36 +00:00
hierarchy Add "hierarchy -chparam" support for non-verific top modules 2019-05-03 22:03:43 +02:00
memory memory_bram: Fix multiport make_transp 2019-04-07 16:56:31 +01:00
opt Merge pull request #1026 from YosysHQ/clifford/fix1023 2019-05-27 13:24:19 +02:00
pmgen Bugfix in peepopt_shiftmul.pmg 2019-05-06 15:34:19 +02:00
proc Improve proc full_case detection and handling, fixes #931 2019-04-18 15:13:47 +02:00
sat Add "fmcombine -initeq -anyeq" 2019-05-11 09:28:55 +02:00
techmap Fix two instances of integer-assignment to string. 2019-05-14 22:01:15 -07:00
tests flowmap: implement depth relaxation. 2019-01-08 01:13:05 +00:00