mirror of https://github.com/YosysHQ/yosys.git
108 lines
2.6 KiB
Verilog
108 lines
2.6 KiB
Verilog
module bram_tb #(
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parameter ABITS = 8, DBITS = 8
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);
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reg clk;
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reg [ABITS-1:0] WR_ADDR;
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reg [DBITS-1:0] WR_DATA;
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reg WR_EN;
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reg [ABITS-1:0] RD_ADDR;
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wire [DBITS-1:0] RD_DATA;
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bram uut (
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.clk (clk ),
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.WR_ADDR(WR_ADDR),
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.WR_DATA(WR_DATA),
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.WR_EN (WR_EN ),
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.RD_ADDR(RD_ADDR),
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.RD_DATA(RD_DATA)
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);
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reg [63:0] xorshift64_state = 64'd88172645463325252 ^ (ABITS << 24) ^ (DBITS << 16);
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task xorshift64_next;
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begin
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// see page 4 of Marsaglia, George (July 2003). "Xorshift RNGs". Journal of Statistical Software 8 (14).
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xorshift64_state = xorshift64_state ^ (xorshift64_state << 13);
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xorshift64_state = xorshift64_state ^ (xorshift64_state >> 7);
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xorshift64_state = xorshift64_state ^ (xorshift64_state << 17);
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end
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endtask
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reg [ABITS-1:0] randaddr1;
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reg [ABITS-1:0] randaddr2;
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reg [ABITS-1:0] randaddr3;
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function [31:0] getaddr(input [3:0] n);
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begin
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case (n)
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0: getaddr = 0;
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1: getaddr = 2**ABITS-1;
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2: getaddr = 'b101 << (ABITS / 3);
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3: getaddr = 'b101 << (2*ABITS / 3);
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4: getaddr = 'b11011 << (ABITS / 4);
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5: getaddr = 'b11011 << (2*ABITS / 4);
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6: getaddr = 'b11011 << (3*ABITS / 4);
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7: getaddr = randaddr1;
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8: getaddr = randaddr2;
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9: getaddr = randaddr3;
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default: begin
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getaddr = 1 << (2*n-16);
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if (!getaddr) getaddr = xorshift64_state;
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end
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endcase
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end
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endfunction
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reg [DBITS-1:0] memory [0:2**ABITS-1];
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reg [DBITS-1:0] expected_rd, expected_rd_masked;
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event error;
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integer i, j;
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initial begin
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// $dumpfile("testbench.vcd");
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// $dumpvars(0, bram_tb);
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xorshift64_next;
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xorshift64_next;
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xorshift64_next;
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xorshift64_next;
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randaddr1 = xorshift64_state;
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xorshift64_next;
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randaddr2 = xorshift64_state;
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xorshift64_next;
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randaddr3 = xorshift64_state;
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xorshift64_next;
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clk <= 0;
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for (i = 0; i < 512; i = i+1) begin
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WR_DATA = xorshift64_state;
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xorshift64_next;
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WR_ADDR = getaddr(i < 256 ? i[7:4] : xorshift64_state[63:60]);
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xorshift64_next;
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RD_ADDR = getaddr(i < 256 ? i[3:0] : xorshift64_state[59:56]);
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WR_EN = xorshift64_state[55] && (WR_ADDR != RD_ADDR);
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xorshift64_next;
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#1; clk <= 1;
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#1; clk <= 0;
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expected_rd = memory[RD_ADDR];
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if (WR_EN) memory[WR_ADDR] = WR_DATA;
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for (j = 0; j < DBITS; j = j+1)
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expected_rd_masked[j] = expected_rd[j] !== 1'bx ? expected_rd[j] : RD_DATA[j];
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$display("#OUT# %3d | WA=%x WD=%x WE=%x | RA=%x RD=%x (%x) | %s",
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i, WR_ADDR, WR_DATA, WR_EN, RD_ADDR, RD_DATA, expected_rd,
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expected_rd_masked === RD_DATA ? "ok" : "ERROR");
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if (expected_rd_masked !== RD_DATA) begin -> error; end
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end
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end
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endmodule
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