yosys/passes
Martin Povišer d6566eb344 booth: Redo baseline architecture summation
Redo the summation logic: strive for some degree of balance on the
generated Wallace tree, emit an `$add` cell for the final summation.
2023-11-22 15:47:11 +01:00
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cmds
equiv
fsm
hierarchy
memory
opt
pmgen
proc
sat
techmap booth: Redo baseline architecture summation 2023-11-22 15:47:11 +01:00
tests