mirror of https://github.com/YosysHQ/yosys.git
d1b86d2fcf
Move additional notes up to the top and give it its own section. Also reformat some paragraphs, and turn some bullet points into paragraphs. Split supported patterns section into some kind of grouping. Currently: - SDP - single-port RAM - reset patterns - asymmetric - TDP |
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| .. | ||
| APPNOTE_011_Design_Investigation | ||
| CHAPTER_Prog | ||
| appendix | ||
| CHAPTER_Approach.rst | ||
| CHAPTER_Basics.rst | ||
| CHAPTER_CellLib.rst | ||
| CHAPTER_Eval.rst | ||
| CHAPTER_Intro.rst | ||
| CHAPTER_Memorymap.rst | ||
| CHAPTER_Optimize.rst | ||
| CHAPTER_Overview.rst | ||
| CHAPTER_Prog.rst | ||
| CHAPTER_Techmap.rst | ||
| CHAPTER_Verilog.rst | ||
| bib.rst | ||
| cmd_ref.rst | ||
| conf.py | ||
| index.rst | ||
| literature.bib | ||
| requirements.txt | ||