mirror of https://github.com/YosysHQ/yosys.git
30 lines
653 B
Verilog
30 lines
653 B
Verilog
(* abc9_box *)
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module $__ABC9_DELAY (input I, output O);
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parameter DELAY = 0;
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specify
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(I => O) = DELAY;
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endspecify
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endmodule
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module $__ABC9_SCC_BREAKER (input [WIDTH-1:0] I, output [WIDTH-1:0] O);
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parameter WIDTH = 0;
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endmodule
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(* abc9_flop, abc9_box, lib_whitebox *)
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module $__DFF_N__$abc9_flop (input C, D, Q, output n1);
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assign n1 = D;
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specify
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$setup(D, posedge C, 0);
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(posedge C => (n1:D)) = 0;
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endspecify
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endmodule
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(* abc9_flop, abc9_box, lib_whitebox *)
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module $__DFF_P__$abc9_flop (input C, D, Q, output n1);
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assign n1 = D;
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specify
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$setup(D, posedge C, 0);
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(posedge C => (n1:D)) = 0;
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endspecify
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endmodule
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