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riscv
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yosys
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https://github.com/YosysHQ/yosys.git
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489caf32c5
yosys
/
techlibs
History
Andrew Zonenberg
489caf32c5
Initial work on greenpak4 counter extraction. Doesn't work but a decent start
2016-03-30 01:07:20 -07:00
..
common
Added more cell help messages
2016-03-29 15:14:43 +02:00
greenpak4
Initial work on greenpak4 counter extraction. Doesn't work but a decent start
2016-03-30 01:07:20 -07:00
ice40
Work around DDR dout sim glitches in ice40 SB_IO sim model
2016-02-07 11:19:48 +01:00
xilinx
Added black box modules for all the 7-series design elements (as listed in ug953)
2016-03-19 11:09:10 +01:00
.gitignore
added .gitignore files
2013-01-05 11:19:11 +01:00