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21 lines
701 B
Plaintext
21 lines
701 B
Plaintext
read_verilog ../common/lutram.v
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hierarchy -top lutram_1w1r
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proc
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memory -nomap
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equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic
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memory
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opt -full
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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#ERROR: Failed to import cell gate.mem.0.0.0 (type EG_LOGIC_DRAM16X4) to SAT database.
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#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
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design -load postopt
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cd lutram_1w1r
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select -assert-count 4 t:AL_MAP_LUT3
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select -assert-count 8 t:AL_MAP_LUT6
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select -assert-count 8 t:AL_MAP_SEQ
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select -assert-count 8 t:EG_LOGIC_DRAM16X4 #Why not AL_LOGIC_BRAM?
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select -assert-none t:AL_MAP_LUT3 t:AL_MAP_LUT6 t:AL_MAP_SEQ t:EG_LOGIC_DRAM16X4 %% t:* %D
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