mirror of https://github.com/YosysHQ/yosys.git
94 lines
4.2 KiB
Verilog
94 lines
4.2 KiB
Verilog
module \$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
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parameter CFG_ABITS = 8;
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parameter CFG_DBITS = 36;
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parameter ABITS = "1";
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parameter DBITS = "1";
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parameter CLKPOL2 = 1;
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parameter CLKPOL3 = 1;
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input CLK2;
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input CLK3;
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//Read data
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output [CFG_DBITS-1:0] A1DATA;
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input [CFG_ABITS-1:0] A1ADDR;
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input A1EN;
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//Write data
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output [CFG_DBITS-1:0] B1DATA;
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input [CFG_ABITS-1:0] B1ADDR;
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input B1EN;
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wire [CFG_DBITS-1:0] B1DATA_t;
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localparam MODE = CFG_DBITS == 1 ? 1:
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CFG_DBITS == 2 ? 2:
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CFG_DBITS == 4 ? 3:
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CFG_DBITS == 8 ? 4:
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CFG_DBITS == 9 ? 5:
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CFG_DBITS == 16 ? 6:
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CFG_DBITS == 18 ? 7:
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CFG_DBITS == 32 ? 8:
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CFG_DBITS == 36 ? 9:
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'bx;
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localparam NUMWORDS = CFG_DBITS == 1 ? 8192:
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CFG_DBITS == 2 ? 4096:
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CFG_DBITS == 4 ? 2048:
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CFG_DBITS == 8 ? 1024:
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CFG_DBITS == 9 ? 1024:
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CFG_DBITS == 16 ? 512:
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CFG_DBITS == 18 ? 512:
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CFG_DBITS == 32 ? 256:
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CFG_DBITS == 36 ? 256:
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'bx;
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altsyncram #(.clock_enable_input_b ("ALTERNATE" ),
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.clock_enable_input_a ("ALTERNATE" ),
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.clock_enable_output_b ("NORMAL" ),
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.clock_enable_output_a ("NORMAL" ),
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.wrcontrol_aclr_a ("NONE" ),
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.indata_aclr_a ("NONE" ),
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.address_aclr_a ("NONE" ),
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.outdata_aclr_a ("NONE" ),
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.outdata_reg_a ("UNREGISTERED"),
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.operation_mode ("SINGLE_PORT" ),
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.intended_device_family ("CYCLONE IVE" ),
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.outdata_reg_a ("UNREGISTERED"),
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.lpm_type ("altsyncram" ),
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.init_type ("unused" ),
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.ram_block_type ("AUTO" ),
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.lpm_hint ("ENABLE_RUNTIME_MOD=NO"), // Forced value
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.power_up_uninitialized ("FALSE"),
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.read_during_write_mode_port_a ("NEW_DATA_NO_NBE_READ"), // Forced value
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.width_byteena_a (1), // Forced value
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.numwords_b ( NUMWORDS ),
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.numwords_a ( NUMWORDS ),
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.widthad_b ( CFG_ABITS ),
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.width_b ( CFG_DBITS ),
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.widthad_a ( CFG_ABITS ),
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.width_a ( CFG_DBITS )
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) _TECHMAP_REPLACE_ (
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.data_a(B1DATA),
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.address_a(B1ADDR),
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.wren_a(B1EN),
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.rden_a(A1EN),
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.q_a(A1DATA),
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.data_b(1'b0),
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.address_b(0),
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.wren_b(1'b0),
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.rden_b(1'b0),
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.q_b(1'b0),
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.clock0(CLK2),
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.clock1(1'b1), // Unused in single port mode
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.clocken0(1'b1),
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.clocken1(1'b1),
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.clocken2(1'b1),
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.clocken3(1'b1),
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.aclr0(1'b0),
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.aclr1(1'b0),
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.addressstall_a(1'b0),
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.addressstall_b(1'b0));
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endmodule
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