yosys/frontends
Kamil Rakoczy 61501e3266 Fix input/output attributes when resolving typedef of wire
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2021-01-18 17:31:22 +01:00
..
aiger Remove YS_ATTRIBUTE(unused) where present just for log_assert()/log_debug(). 2020-06-19 15:48:58 +00:00
ast Fix input/output attributes when resolving typedef of wire 2021-01-18 17:31:22 +01:00
blif Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
json Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
liberty Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
rpc Fix argument handling in connect_rpc 2020-10-19 13:40:57 +02:00
rtlil rtlil: remove dotted identifiers. 2020-11-25 16:47:20 +00:00
verific Bump required Verific version 2020-12-02 15:18:04 +01:00
verilog Parse package user type in module port list 2021-01-18 17:31:22 +01:00