mirror of https://github.com/YosysHQ/yosys.git
226 lines
4.7 KiB
Plaintext
226 lines
4.7 KiB
Plaintext
read_verilog << EOT
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// FDRE, mergeable CE and R.
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module t0 (...);
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input wire clk;
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input wire [7:0] i;
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output wire [7:0] o;
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wire [7:0] tmp ;
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LUT2 #(.INIT(4'h6)) lut0 (.I0(i[0]), .I1(i[1]), .O(tmp[0]));
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LUT2 #(.INIT(4'h6)) lut1 (.I0(i[1]), .I1(i[2]), .O(tmp[1]));
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LUT2 #(.INIT(4'h6)) lut2 (.I0(i[3]), .I1(i[4]), .O(tmp[2]));
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FDRE ff (.D(tmp[0]), .CE(tmp[1]), .R(tmp[2]), .Q(o[0]));
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endmodule
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EOT
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read_verilog -lib +/xilinx/cells_sim.v
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design -save t0
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equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt
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design -load postopt
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clean
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cd t0
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select -assert-count 1 t:FDRE
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select -assert-count 1 t:LUT6
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select -assert-none t:FDRE t:LUT6 %% t:* %D
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design -load t0
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equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt -lut4
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design -load postopt
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clean
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cd t0
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select -assert-count 1 t:FDRE
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select -assert-count 1 t:LUT4
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select -assert-count 1 t:LUT2
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select -assert-none t:FDRE t:LUT4 t:LUT2 %% t:* %D
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design -reset
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read_verilog << EOT
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// FDSE, mergeable CE and S, inversions.
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module t0 (...);
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input wire clk;
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input wire [7:0] i;
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output wire [7:0] o;
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wire [7:0] tmp ;
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LUT2 #(.INIT(4'h6)) lut0 (.I0(i[0]), .I1(i[1]), .O(tmp[0]));
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LUT2 #(.INIT(4'h6)) lut1 (.I0(i[1]), .I1(i[2]), .O(tmp[1]));
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LUT2 #(.INIT(4'h6)) lut2 (.I0(i[3]), .I1(i[4]), .O(tmp[2]));
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FDSE #(.IS_D_INVERTED(1'b1), .IS_S_INVERTED(1'b1)) ff (.D(tmp[0]), .CE(tmp[1]), .S(tmp[2]), .Q(o[0]));
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endmodule
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EOT
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read_verilog -lib +/xilinx/cells_sim.v
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design -save t0
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equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt
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design -load postopt
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clean
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cd t0
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select -assert-count 1 t:FDSE
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select -assert-count 1 t:LUT6
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select -assert-none t:FDSE t:LUT6 %% t:* %D
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design -load t0
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equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt -lut4
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design -load postopt
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clean
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cd t0
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select -assert-count 1 t:FDSE
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select -assert-count 1 t:LUT4
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select -assert-count 1 t:LUT2
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select -assert-none t:FDSE t:LUT4 t:LUT2 %% t:* %D
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design -reset
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read_verilog << EOT
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// FDCE, mergeable CE.
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module t0 (...);
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input wire clk;
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input wire [7:0] i;
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output wire [7:0] o;
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wire [7:0] tmp ;
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LUT2 #(.INIT(4'h6)) lut0 (.I0(i[0]), .I1(i[1]), .O(tmp[0]));
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LUT2 #(.INIT(4'h6)) lut1 (.I0(i[1]), .I1(i[2]), .O(tmp[1]));
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LUT2 #(.INIT(4'h6)) lut2 (.I0(i[3]), .I1(i[4]), .O(tmp[2]));
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FDCE ff (.D(tmp[0]), .CE(tmp[1]), .CLR(tmp[2]), .Q(o[0]));
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endmodule
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EOT
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read_verilog -lib +/xilinx/cells_sim.v
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design -save t0
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equiv_opt -async2sync -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt
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design -load postopt
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clean
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cd t0
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select -assert-count 1 t:FDCE
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select -assert-count 1 t:LUT4
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select -assert-count 1 t:LUT2
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select -assert-none t:FDCE t:LUT4 t:LUT2 %% t:* %D
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design -reset
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read_verilog << EOT
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// FDSE, mergeable CE and S, but CE only not worth it.
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module t0 (...);
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input wire clk;
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input wire [7:0] i;
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output wire [7:0] o;
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wire [7:0] tmp ;
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LUT2 #(.INIT(4'h6)) lut0 (.I0(i[0]), .I1(i[1]), .O(tmp[0]));
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LUT2 #(.INIT(4'h6)) lut1 (.I0(i[1]), .I1(i[2]), .O(tmp[1]));
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FDSE ff (.D(tmp[0]), .CE(i[7]), .S(tmp[1]), .Q(o[0]));
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endmodule
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EOT
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read_verilog -lib +/xilinx/cells_sim.v
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design -save t0
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equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt
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design -load postopt
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clean
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cd t0
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select -assert-count 1 t:FDSE
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select -assert-count 1 t:LUT5
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select -assert-none t:FDSE t:LUT5 %% t:* %D
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design -load t0
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equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt -lut4
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design -load postopt
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clean
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cd t0
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select -assert-count 1 t:FDSE
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select -assert-count 2 t:LUT2
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select -assert-none t:FDSE t:LUT2 %% t:* %D
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design -reset
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read_verilog << EOT
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// FDRSE, mergeable CE, S, R.
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module t0 (...);
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input wire clk;
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input wire [7:0] i;
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output wire [7:0] o;
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wire [7:0] tmp ;
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LUT2 #(.INIT(4'h6)) lut0 (.I0(i[0]), .I1(i[1]), .O(tmp[0]));
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LUT2 #(.INIT(4'h6)) lut1 (.I0(i[1]), .I1(i[2]), .O(tmp[1]));
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LUT2 #(.INIT(4'h8)) lut2 (.I0(i[2]), .I1(i[0]), .O(tmp[2]));
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LUT2 #(.INIT(4'h6)) lut3 (.I0(i[3]), .I1(i[4]), .O(tmp[3]));
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FDRSE ff (.D(tmp[0]), .CE(tmp[1]), .S(tmp[2]), .R(tmp[3]), .Q(o[0]));
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endmodule
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EOT
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read_verilog -lib +/xilinx/cells_sim.v
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design -save t0
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equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt
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design -load postopt
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clean
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cd t0
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select -assert-count 1 t:FDRSE
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select -assert-count 1 t:LUT6
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select -assert-none t:FDRSE t:LUT6 %% t:* %D
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design -load t0
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equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt -lut4
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design -load postopt
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clean
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cd t0
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select -assert-count 1 t:FDRSE
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select -assert-count 1 t:LUT4
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select -assert-count 1 t:LUT2
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select -assert-none t:FDRSE t:LUT4 t:LUT2 %% t:* %D
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design -reset
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