mirror of https://github.com/YosysHQ/yosys.git
30 lines
424 B
Verilog
30 lines
424 B
Verilog
(* abc9_box_id = 1, lib_whitebox *)
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module \$__ICE40_CARRY_WRAPPER (
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(* abc9_carry *)
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output CO,
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output O,
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input A, B,
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(* abc9_carry *)
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input CI,
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input I0, I3
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);
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parameter LUT = 0;
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parameter I3_IS_CI = 0;
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wire I3_OR_CI = I3_IS_CI ? CI : I3;
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SB_CARRY carry (
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.I0(A),
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.I1(B),
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.CI(CI),
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.CO(CO)
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);
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SB_LUT4 #(
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.LUT_INIT(LUT)
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) adder (
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.I0(I0),
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.I1(A),
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.I2(B),
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.I3(I3_OR_CI),
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.O(O)
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);
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endmodule
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