Clifford Wolf e605af8a49 Fixed Verilog pre-processor for files with no trailing newline		2014-07-29 20:14:25 +02:00
..
.gitignore	added .gitignore files	2013-01-05 11:19:11 +01:00
Makefile.inc	Added "make PRETTY=1"	2014-07-24 17:15:01 +02:00
const2ast.cc	Using log_assert() instead of assert()	2014-07-28 11:27:48 +02:00
lexer.l	Added handling of real-valued parameters/localparams	2014-06-14 12:00:47 +02:00
parser.y	fixed parsing of constant with comment between size and value	2014-07-02 06:27:04 +02:00
preproc.cc	Fixed Verilog pre-processor for files with no trailing newline	2014-07-29 20:14:25 +02:00
verilog_frontend.cc	Using log_assert() instead of assert()	2014-07-28 11:27:48 +02:00
verilog_frontend.h	Added read_verilog -sv options, added support for bit, logic,	2014-06-12 11:54:20 +02:00