mirror of https://github.com/YosysHQ/yosys.git
145 lines
4.6 KiB
Verilog
145 lines
4.6 KiB
Verilog
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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module VCC (output V);
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assign V = 1'b1;
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endmodule // VCC
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module GND (output G);
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assign G = 1'b0;
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endmodule // GND
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/* Altera Cyclone V devices Input Buffer Primitive */
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module cyclonev_io_ibuf
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(output o, input i, input ibar);
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assign ibar = ibar;
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assign o = i;
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endmodule // cyclonev_io_ibuf
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/* Altera Cyclone V devices Output Buffer Primitive */
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module cyclonev_io_obuf
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(output o, input i, input oe);
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assign o = i;
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assign oe = oe;
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endmodule // cyclonev_io_obuf
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/* Altera Cyclone V LUT Primitive */
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module cyclonev_lcell_comb
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(output combout, cout, sumout, shareout,
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input dataa, datab, datac, datad,
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input datae, dataf, datag, cin,
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input sharein);
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parameter lut_mask = 64'hFFFFFFFFFFFFFFFF;
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parameter dont_touch = "off";
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parameter lpm_type = "cyclonev_lcell_comb";
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parameter shared_arith = "off";
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parameter extended_lut = "off";
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// Internal variables
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// Sub mask for fragmented LUTs
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wire [15:0] mask_a, mask_b, mask_c, mask_d;
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// Independant output for fragmented LUTs
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wire output_0, output_1, output_2, output_3;
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// Extended mode uses mux to define the output
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wire mux_0, mux_1;
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// Input for hold the shared LUT mode value
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wire shared_lut_alm;
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// Simulation model of 4-input LUT
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function lut4;
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input [15:0] mask;
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input dataa, datab, datac, datad;
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reg [7:0] s3;
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reg [3:0] s2;
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reg [1:0] s1;
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begin
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s3 = datad ? mask[15:8] : mask[7:0];
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s2 = datac ? s3[7:4] : s3[3:0];
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s1 = datab ? s2[3:2] : s2[1:0];
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lut4 = dataa ? s1[1] : s1[0];
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end
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endfunction // lut4
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// Simulation model of 5-input LUT
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function lut5;
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input [31:0] mask; // wp-01003.pdf, page 3: "a 5-LUT can be built with two 4-LUTs and a multiplexer.
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input dataa, datab, datac, datad, datae;
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reg upper_lut_value;
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reg lower_lut_value;
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begin
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upper_lut_value = lut4(mask[31:16], dataa, datab, datac, datad);
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lower_lut_value = lut4(mask[15:0], dataa, datab, datac, datad);
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lut5 = (datae) ? upper_mask_value : lower_mask_value;
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end
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endfunction // lut5
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// Simulation model of 6-input LUT
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function lut6;
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input [63:0] mask;
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input dataa, datab, datac, datad, datae, dataf;
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reg upper_lut_value;
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reg lower_lut_value;
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begin
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upper_lut_value = lut5(mask[63:32], dataa, datab, datac, datad, datae);
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lower_lut_value = lut5(mask[31:0], dataa, datab, datac, datad, datae);
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lut6 = (dataf) ? upper_mask_value : lower_mask_value;
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end
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endfunction // lut6
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assign {mask_a, mask_b, mask_c, mask_d} = {lut_mask[15:0], lut_mask[31:16], lut_mask[47:32], lut_mask[63:48]};
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always @(*) begin
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if(extended_lut == "on")
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shared_lut_alm = datag;
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else
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shared_lut_alm = datac;
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// Build the ALM behaviour
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out_0 = lut4(mask_a, dataa, datab, datac, datad);
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out_1 = lut4(mask_b, dataa, datab, shared_lut_alm, datad);
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out_2 = lut4(mask_c, dataa, datab, datac, datad);
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out_3 = lut4(mask_d, dataa, datab, shared_lut_alm, datad);
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end
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endmodule // cyclonev_lcell_comb
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/* Altera D Flip-Flop Primitive */
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module dffeas
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(output q,
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input d, clk, clrn, prn, ena,
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input asdata, aload, sclr, sload);
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// Timing simulation is not covered
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parameter power_up="dontcare";
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parameter is_wysiwyg="false";
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reg q_tmp;
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wire reset;
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reg [7:0] debug_net;
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assign reset = (prn && sclr && ~clrn && ena);
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assign q = q_tmp & 1'b1;
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always @(posedge clk, posedge aload) begin
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if(reset) q_tmp <= 0;
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else q_tmp <= d;
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end
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assign q = q_tmp;
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endmodule // dffeas
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