mirror of https://github.com/YosysHQ/yosys.git
55 lines
1.4 KiB
Verilog
55 lines
1.4 KiB
Verilog
//-----------------------------------------------------
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// Design Name : clk_div_45
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// File Name : clk_div_45.v
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// Function : Divide by 4.5
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// Coder : Deepak Kumar Tala
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//-----------------------------------------------------
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module clk_div_45 (
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clk_in, // Input Clock
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enable, // Enable is sync with falling edge of clk_in
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clk_out // Output Clock
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);
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// --------------Port Declaration-----------------------
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input clk_in ;
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input enable ;
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output clk_out ;
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//--------------Port data type declaration-------------
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wire clk_in ;
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wire enable ;
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wire clk_out ;
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//--------------Internal Registers----------------------
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reg [3:0] counter1 ;
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reg [3:0] counter2 ;
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reg toggle1 ;
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reg toggle2 ;
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//--------------Code Starts Here-----------------------
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always @ (posedge clk_in)
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if (enable == 1'b0) begin
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counter1 <= 4'b0;
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toggle1 <= 0;
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end else if ((counter1 == 3 && toggle2) || (~toggle1 && counter1 == 4)) begin
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counter1 <= 4'b0;
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toggle1 <= ~toggle1;
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end else begin
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counter1 <= counter1 + 1;
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end
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always @ (negedge clk_in)
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if (enable == 1'b0) begin
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counter2 <= 4'b0;
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toggle2 <= 0;
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end else if ((counter2 == 3 && ~toggle2) || (toggle2 && counter2 == 4)) begin
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counter2 <= 4'b0;
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toggle2 <= ~toggle2;
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end else begin
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counter2 <= counter2 + 1;
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end
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assign clk_out = (counter1 <3 && counter2 < 3) & enable;
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endmodule
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