mirror of https://github.com/YosysHQ/yosys.git
20 lines
388 B
Verilog
20 lines
388 B
Verilog
(* abc_box_id = 1 *)
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module MUXF7(output O, input I0, I1, S);
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assign O = S ? I1 : I0;
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endmodule
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(* abc_box_id = 2 *)
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module MUXF8(output O, input I0, I1, S);
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assign O = S ? I1 : I0;
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endmodule
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(* abc_box_id = 3 *)
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module MUXCY(output O, input CI, DI, S);
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assign O = S ? CI : DI;
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endmodule
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(* abc_box_id = 4 *)
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module XORCY(output O, input CI, LI);
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assign O = CI ^ LI;
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endmodule
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