yosys/passes
Eddie Hung fc5fda595d Merge branch 'xaig' into xc7mux 2019-04-16 13:15:53 -07:00
..
cmds For 'stat' do not count modules with abc_box_id 2019-04-16 11:19:54 -07:00
equiv Fix equiv_opt indenting 2018-12-16 15:57:28 +01:00
fsm fsm_opt: Fix runtime error for FSMs without a reset state 2019-02-07 10:35:36 +00:00
hierarchy Add "hdlname" attribute 2019-03-26 14:52:48 +01:00
memory memory_bram: Fix multiport make_transp 2019-04-07 16:56:31 +01:00
opt Trim init attributes when resizing FFs in "wreduce", fixes #887 2019-03-22 11:42:19 +01:00
pmgen Fix a few typos 2019-04-08 16:46:33 -07:00
proc Revert "Recognise default entry in case even if all cases covered (fix for #931)" 2019-04-15 17:52:45 -07:00
sat Merge branch 'master' into xaig 2019-04-08 16:31:59 -07:00
techmap Merge branch 'xaig' into xc7mux 2019-04-16 13:15:53 -07:00
tests flowmap: implement depth relaxation. 2019-01-08 01:13:05 +00:00