mirror of https://github.com/YosysHQ/yosys.git
287 lines
8.2 KiB
C++
287 lines
8.2 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/celltypes.h"
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#include "kernel/rtlil.h"
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#include "kernel/log.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct SplitnetsWorker
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{
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std::map<RTLIL::Wire*, std::vector<RTLIL::SigBit>> splitmap;
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void append_wire(RTLIL::Module *module, RTLIL::Wire *wire, int offset, int width, std::string format)
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{
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std::string new_wire_name = wire->name.str();
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if (format.size() > 0)
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new_wire_name += format.substr(0, 1);
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if (width > 1) {
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if (wire->upto)
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new_wire_name += stringf("%d", wire->start_offset+wire->width-(offset+width)-1);
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else
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new_wire_name += stringf("%d", wire->start_offset+offset+width-1);
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if (format.size() > 2)
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new_wire_name += format.substr(2, 1);
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else
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new_wire_name += ":";
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}
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if (wire->upto)
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new_wire_name += stringf("%d", wire->start_offset+wire->width-offset-1);
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else
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new_wire_name += stringf("%d", wire->start_offset+offset);
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if (format.size() > 1)
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new_wire_name += format.substr(1, 1);
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RTLIL::Wire *new_wire = module->addWire(module->uniquify(new_wire_name), width);
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new_wire->port_id = wire->port_id ? wire->port_id + offset : 0;
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new_wire->port_input = wire->port_input;
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new_wire->port_output = wire->port_output;
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new_wire->start_offset = wire->start_offset + offset;
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auto it = wire->attributes.find(ID::src);
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if (it != wire->attributes.end())
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new_wire->attributes.emplace(ID::src, it->second);
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it = wire->attributes.find(ID::hdlname);
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if (it != wire->attributes.end())
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new_wire->attributes.emplace(ID::hdlname, it->second);
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it = wire->attributes.find(ID::keep);
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if (it != wire->attributes.end())
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new_wire->attributes.emplace(ID::keep, it->second);
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it = wire->attributes.find(ID::init);
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if (it != wire->attributes.end()) {
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Const old_init = it->second, new_init;
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for (int i = offset; i < offset+width; i++)
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new_init.bits.push_back(i < GetSize(old_init) ? old_init.bits.at(i) : State::Sx);
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new_wire->attributes.emplace(ID::init, new_init);
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}
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std::vector<RTLIL::SigBit> sigvec = RTLIL::SigSpec(new_wire).to_sigbit_vector();
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splitmap[wire].insert(splitmap[wire].end(), sigvec.begin(), sigvec.end());
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}
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void operator()(RTLIL::SigSpec &sig)
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{
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for (auto &bit : sig)
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if (splitmap.count(bit.wire) > 0)
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bit = splitmap.at(bit.wire).at(bit.offset);
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}
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};
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struct SplitnetsPass : public Pass {
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SplitnetsPass() : Pass("splitnets", "split up multi-bit nets") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" splitnets [options] [selection]\n");
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log("\n");
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log("This command splits multi-bit nets into single-bit nets.\n");
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log("\n");
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log(" -format char1[char2[char3]]\n");
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log(" the first char is inserted between the net name and the bit index, the\n");
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log(" second char is appended to the netname. e.g. -format () creates net\n");
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log(" names like 'mysignal(42)'. the 3rd character is the range separation\n");
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log(" character when creating multi-bit wires. the default is '[]:'.\n");
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log("\n");
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log(" -ports\n");
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log(" also split module ports. per default only internal signals are split.\n");
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log("\n");
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log(" -driver\n");
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log(" don't blindly split nets in individual bits. instead look at the driver\n");
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log(" and split nets so that no driver drives only part of a net.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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bool flag_ports = false;
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bool flag_driver = false;
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std::string format = "[]:";
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log_header(design, "Executing SPLITNETS pass (splitting up multi-bit signals).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-format" && argidx+1 < args.size()) {
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format = args[++argidx];
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continue;
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}
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if (args[argidx] == "-ports") {
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flag_ports = true;
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continue;
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}
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if (args[argidx] == "-driver") {
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flag_driver = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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// module_ports_db[module_name][old_port_name] = new_port_name_list
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dict<IdString, dict<IdString, vector<IdString>>> module_ports_db;
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for (auto module : design->selected_modules())
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{
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if (module->has_processes_warn())
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continue;
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SplitnetsWorker worker;
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if (flag_ports)
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{
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int normalized_port_factor = 0;
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for (auto wire : module->wires())
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if (wire->port_id != 0) {
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normalized_port_factor = max(normalized_port_factor, wire->port_id+1);
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normalized_port_factor = max(normalized_port_factor, GetSize(wire)+1);
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}
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for (auto wire : module->wires())
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wire->port_id *= normalized_port_factor;
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}
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if (flag_driver)
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{
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CellTypes ct(design);
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std::map<RTLIL::Wire*, std::set<int>> split_wires_at;
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for (auto c : module->cells())
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for (auto &p : c->connections())
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{
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if (!ct.cell_known(c->type))
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continue;
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if (!ct.cell_output(c->type, p.first))
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continue;
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RTLIL::SigSpec sig = p.second;
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for (auto &chunk : sig.chunks()) {
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if (chunk.wire == NULL)
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continue;
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if (chunk.wire->port_id == 0 || flag_ports) {
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if (chunk.offset != 0)
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split_wires_at[chunk.wire].insert(chunk.offset);
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if (chunk.offset + chunk.width < chunk.wire->width)
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split_wires_at[chunk.wire].insert(chunk.offset + chunk.width);
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}
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}
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}
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for (auto &it : split_wires_at) {
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int cursor = 0;
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for (int next_cursor : it.second) {
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worker.append_wire(module, it.first, cursor, next_cursor - cursor, format);
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cursor = next_cursor;
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}
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worker.append_wire(module, it.first, cursor, it.first->width - cursor, format);
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}
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}
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else
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{
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for (auto wire : module->wires()) {
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if (wire->width > 1 && (wire->port_id == 0 || flag_ports) && design->selected(module, wire))
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worker.splitmap[wire] = std::vector<RTLIL::SigBit>();
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}
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for (auto &it : worker.splitmap)
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for (int i = 0; i < it.first->width; i++)
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worker.append_wire(module, it.first, i, 1, format);
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}
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module->rewrite_sigspecs(worker);
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if (flag_ports)
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{
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for (auto wire : module->wires())
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{
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if (wire->port_id == 0)
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continue;
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SigSpec sig(wire);
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worker(sig);
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if (sig == wire)
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continue;
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vector<IdString> &new_ports = module_ports_db[module->name][wire->name];
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for (SigSpec c : sig.chunks())
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new_ports.push_back(c.as_wire()->name);
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}
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}
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pool<RTLIL::Wire*> delete_wires;
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for (auto &it : worker.splitmap)
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delete_wires.insert(it.first);
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module->remove(delete_wires);
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if (flag_ports)
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module->fixup_ports();
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}
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if (!module_ports_db.empty())
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{
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for (auto module : design->modules())
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for (auto cell : module->cells())
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{
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if (module_ports_db.count(cell->type) == 0)
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continue;
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for (auto &it : module_ports_db.at(cell->type))
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{
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IdString port_id = it.first;
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const auto &new_port_ids = it.second;
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if (!cell->hasPort(port_id))
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continue;
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int offset = 0;
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SigSpec sig = cell->getPort(port_id);
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for (auto nid : new_port_ids)
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{
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int nlen = GetSize(design->module(cell->type)->wire(nid));
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if (offset + nlen > GetSize(sig))
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nlen = GetSize(sig) - offset;
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if (nlen > 0)
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cell->setPort(nid, sig.extract(offset, nlen));
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offset += nlen;
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}
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cell->unsetPort(port_id);
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}
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}
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}
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}
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} SplitnetsPass;
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PRIVATE_NAMESPACE_END
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