mirror of https://github.com/YosysHQ/yosys.git
74 lines
2.1 KiB
ReStructuredText
74 lines
2.1 KiB
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:Abstract:
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Most of today's digital design is done in HDL code (mostly Verilog or
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VHDL) and with the help of HDL synthesis tools.
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In special cases such as synthesis for coarse-grain cell libraries or
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when testing new synthesis algorithms it might be necessary to write a
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custom HDL synthesis tool or add new features to an existing one. In
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these cases the availability of a Free and Open Source (FOSS) synthesis
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tool that can be used as basis for custom tools would be helpful.
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In the absence of such a tool, the Yosys Open SYnthesis Suite (Yosys)
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was developed. This document covers the design and implementation of
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this tool. At the moment the main focus of Yosys lies on the high-level
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aspects of digital synthesis. The pre-existing FOSS logic-synthesis tool
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ABC is used by Yosys to perform advanced gate-level optimizations.
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An evaluation of Yosys based on real-world designs is included. It is
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shown that Yosys can be used as-is to synthesize such designs. The
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results produced by Yosys in this tests where successfully verified
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using formal verification and are comparable in quality to the results
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produced by a commercial synthesis tool.
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This document was originally published as bachelor thesis at the Vienna
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University of Technology :cite:p:`BACC`.
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================================================================================
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Yosys manual
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================================================================================
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.. toctree::
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:maxdepth: 2
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:caption: Manual
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:numbered:
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CHAPTER_Intro
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CHAPTER_Basics.rst
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CHAPTER_Approach.rst
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CHAPTER_Overview.rst
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CHAPTER_CellLib.rst
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CHAPTER_Prog.rst
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CHAPTER_Verilog.rst
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CHAPTER_Optimize.rst
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CHAPTER_Techmap.rst
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CHAPTER_Memorymap.rst
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CHAPTER_Eval.rst
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.. raw:: latex
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\appendix
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.. toctree::
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:maxdepth: 2
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:includehidden:
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:caption: Appendix
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appendix/CHAPTER_Auxlibs.rst
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appendix/CHAPTER_Auxprogs.rst
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appendix/CHAPTER_TextRtlil.rst
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appendix/APPNOTE_010_Verilog_to_BLIF.rst
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appendix/APPNOTE_011_Design_Investigation.rst
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appendix/APPNOTE_012_Verilog_to_BTOR.rst
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appendix/CHAPTER_StateOfTheArt.rst
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bib
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.. toctree::
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:maxdepth: 1
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:includehidden:
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cmd_ref
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