mirror of https://github.com/YosysHQ/yosys.git
36 lines
1.2 KiB
Plaintext
36 lines
1.2 KiB
Plaintext
read_verilog ../common/latches.v
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design -save read
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hierarchy -top latchp
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proc
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equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd latchp # Constrain all select calls below inside the top module
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select -assert-count 1 t:LDCE
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select -assert-none t:LDCE t:IBUF t:OBUF %% t:* %D
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design -load read
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hierarchy -top latchn
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proc
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equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd latchn # Constrain all select calls below inside the top module
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select -assert-count 1 t:LDCE
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select -assert-count 1 t:INV
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select -assert-none t:LDCE t:INV t:IBUF t:OBUF %% t:* %D
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design -load read
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hierarchy -top latchsr
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proc
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equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd latchsr # Constrain all select calls below inside the top module
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select -assert-count 1 t:LDCE
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select -assert-count 2 t:LUT3
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select -assert-none t:LDCE t:LUT3 t:IBUF t:OBUF %% t:* %D
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