mirror of https://github.com/YosysHQ/yosys.git
406 lines
13 KiB
C++
406 lines
13 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/celltypes.h"
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#include "kernel/log.h"
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#include "kernel/sigtools.h"
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#include <stdlib.h>
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#include <stdio.h>
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#include <set>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct SubmodWorker
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{
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CellTypes ct;
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RTLIL::Design *design;
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RTLIL::Module *module;
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SigMap sigmap;
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pool<SigBit> outputs;
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bool copy_mode;
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bool hidden_mode;
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std::string opt_name;
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struct SubModule
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{
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std::string name, full_name;
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std::set<RTLIL::Cell*> cells;
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};
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std::map<std::string, SubModule> submodules;
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struct bit_flags_t {
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RTLIL::Wire *new_wire;
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bool is_int_driven, is_int_used, is_ext_driven, is_ext_used;
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bit_flags_t() : new_wire(NULL), is_int_driven(false), is_int_used(false), is_ext_driven(false), is_ext_used(false) { }
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};
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std::map<SigBit, bit_flags_t> bit_flags;
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bool flag_found_something;
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void flag_bit(RTLIL::SigBit bit, bool create, bool set_int_driven, bool set_int_used, bool set_ext_driven, bool set_ext_used)
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{
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if (bit_flags.count(bit) == 0) {
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if (!create)
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return;
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bit_flags[bit] = bit_flags_t();
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}
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if (set_int_driven)
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bit_flags[bit].is_int_driven = true;
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if (set_int_used)
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bit_flags[bit].is_int_used = true;
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if (set_ext_driven)
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bit_flags[bit].is_ext_driven = true;
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if (set_ext_used)
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bit_flags[bit].is_ext_used = true;
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flag_found_something = true;
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}
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void flag_signal(const RTLIL::SigSpec &sig, bool create, bool set_int_driven, bool set_int_used, bool set_ext_driven, bool set_ext_used)
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{
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for (auto &b : sig)
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if (b.wire != NULL)
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flag_bit(b, create, set_int_driven, set_int_used, set_ext_driven, set_ext_used);
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}
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void handle_submodule(SubModule &submod)
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{
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log("Creating submodule %s (%s) of module %s.\n", submod.name.c_str(), submod.full_name.c_str(), module->name.c_str());
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bit_flags.clear();
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for (RTLIL::Cell *cell : submod.cells) {
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if (ct.cell_known(cell->type)) {
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for (auto &conn : cell->connections())
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flag_signal(conn.second, true, ct.cell_output(cell->type, conn.first), ct.cell_input(cell->type, conn.first), false, false);
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} else {
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log_warning("Port directions for cell %s (%s) are unknown. Assuming inout for all ports.\n", cell->name.c_str(), cell->type.c_str());
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for (auto &conn : cell->connections())
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flag_signal(conn.second, true, true, true, false, false);
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}
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}
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for (auto &it : module->cells_) {
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RTLIL::Cell *cell = it.second;
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if (submod.cells.count(cell) > 0)
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continue;
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if (ct.cell_known(cell->type)) {
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for (auto &conn : cell->connections())
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flag_signal(conn.second, false, false, false, ct.cell_output(cell->type, conn.first), ct.cell_input(cell->type, conn.first));
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} else {
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flag_found_something = false;
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for (auto &conn : cell->connections())
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flag_signal(conn.second, false, false, false, true, true);
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if (flag_found_something)
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log_warning("Port directions for cell %s (%s) are unknown. Assuming inout for all ports.\n", cell->name.c_str(), cell->type.c_str());
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}
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}
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RTLIL::Module *new_mod = new RTLIL::Module;
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new_mod->name = submod.full_name;
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design->add(new_mod);
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int auto_name_counter = 1;
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std::set<RTLIL::IdString> all_wire_names;
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for (auto &it : bit_flags) {
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all_wire_names.insert(it.first.wire->name);
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}
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for (auto &it : bit_flags)
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{
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const RTLIL::SigBit &bit = it.first;
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RTLIL::Wire *wire = bit.wire;
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bit_flags_t &flags = it.second;
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if (wire->port_input)
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flags.is_ext_driven = true;
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if (outputs.count(bit))
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flags.is_ext_used = true;
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bool new_wire_port_input = false;
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bool new_wire_port_output = false;
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if (flags.is_int_driven && flags.is_ext_used)
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new_wire_port_output = true;
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if (flags.is_ext_driven && flags.is_int_used)
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new_wire_port_input = true;
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if (flags.is_int_driven && flags.is_ext_driven)
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new_wire_port_input = true, new_wire_port_output = true;
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RTLIL::IdString new_wire_name;
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if (GetSize(wire) == 1)
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new_wire_name = wire->name;
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else
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new_wire_name = stringf("%s[%d]", wire->name.c_str(), bit.offset);
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if (new_wire_port_input || new_wire_port_output) {
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if (new_wire_name[0] == '$')
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do {
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std::string next_wire_name = stringf("%s\\n%d", hidden_mode ? "$submod" : ":", auto_name_counter++);
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if (all_wire_names.count(next_wire_name) == 0) {
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all_wire_names.insert(next_wire_name);
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new_wire_name = next_wire_name;
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}
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} while (new_wire_name[0] == '$');
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else
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new_wire_name = stringf("$submod%s\n", new_wire_name.c_str());
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}
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RTLIL::Wire *new_wire = new_mod->addWire(new_wire_name);
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new_wire->port_input = new_wire_port_input;
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new_wire->port_output = new_wire_port_output;
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new_wire->attributes = wire->attributes;
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if (new_wire->port_output) {
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auto it = wire->attributes.find(ID(init));
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if (it != wire->attributes.end()) {
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new_wire->attributes[ID(init)] = it->second[bit.offset];
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it->second[bit.offset] = State::Sx;
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}
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}
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if (new_wire->port_input && new_wire->port_output)
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log(" signal %s: inout %s\n", wire->name.c_str(), new_wire->name.c_str());
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else if (new_wire->port_input)
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log(" signal %s: input %s\n", wire->name.c_str(), new_wire->name.c_str());
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else if (new_wire->port_output)
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log(" signal %s: output %s\n", wire->name.c_str(), new_wire->name.c_str());
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else
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log(" signal %s: internal\n", wire->name.c_str());
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flags.new_wire = new_wire;
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}
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new_mod->fixup_ports();
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ct.setup_module(new_mod);
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for (RTLIL::Cell *cell : submod.cells) {
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RTLIL::Cell *new_cell = new_mod->addCell(cell->name, cell);
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for (auto &conn : new_cell->connections_)
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for (auto &bit : conn.second)
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if (bit.wire != NULL) {
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log_assert(bit_flags.count(bit) > 0);
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bit = bit_flags[bit].new_wire;
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}
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log(" cell %s (%s)\n", new_cell->name.c_str(), new_cell->type.c_str());
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if (!copy_mode)
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module->remove(cell);
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}
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submod.cells.clear();
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if (!copy_mode) {
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RTLIL::Cell *new_cell = module->addCell(submod.full_name, submod.full_name);
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for (auto &it : bit_flags)
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{
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RTLIL::SigBit old_bit = it.first;
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RTLIL::Wire *new_wire = it.second.new_wire;
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if (new_wire->port_id > 0)
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new_cell->setPort(new_wire->name, old_bit);
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}
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}
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}
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SubmodWorker(RTLIL::Design *design, RTLIL::Module *module, bool copy_mode = false, bool hidden_mode = false, std::string opt_name = std::string()) :
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design(design), module(module), sigmap(module), copy_mode(copy_mode), hidden_mode(hidden_mode), opt_name(opt_name)
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{
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if (!design->selected_whole_module(module->name) && opt_name.empty())
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return;
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if (module->processes.size() > 0) {
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log("Skipping module %s as it contains processes (run 'proc' pass first).\n", module->name.c_str());
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return;
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}
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if (module->memories.size() > 0) {
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log("Skipping module %s as it contains memories (run 'memory' pass first).\n", module->name.c_str());
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return;
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}
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ct.setup_internals();
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ct.setup_internals_mem();
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ct.setup_stdcells();
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ct.setup_stdcells_mem();
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ct.setup_design(design);
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for (auto port : module->ports) {
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auto wire = module->wire(port);
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if (!wire->port_output)
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continue;
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for (auto b : sigmap(wire))
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if (b.wire)
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outputs.insert(b);
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}
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if (opt_name.empty())
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{
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for (auto &it : module->wires_)
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it.second->attributes.erase("\\submod");
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for (auto &it : module->cells_)
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{
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RTLIL::Cell *cell = it.second;
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if (cell->attributes.count("\\submod") == 0 || cell->attributes["\\submod"].bits.size() == 0) {
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cell->attributes.erase("\\submod");
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continue;
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}
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std::string submod_str = cell->attributes["\\submod"].decode_string();
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cell->attributes.erase("\\submod");
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if (submodules.count(submod_str) == 0) {
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submodules[submod_str].name = submod_str;
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submodules[submod_str].full_name = module->name.str() + "_" + submod_str;
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while (design->modules_.count(submodules[submod_str].full_name) != 0 ||
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module->count_id(submodules[submod_str].full_name) != 0)
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submodules[submod_str].full_name += "_";
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}
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submodules[submod_str].cells.insert(cell);
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}
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}
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else
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{
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for (auto &it : module->cells_)
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{
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RTLIL::Cell *cell = it.second;
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if (!design->selected(module, cell))
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continue;
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submodules[opt_name].name = opt_name;
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submodules[opt_name].full_name = RTLIL::escape_id(opt_name);
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submodules[opt_name].cells.insert(cell);
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}
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if (submodules.size() == 0)
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log("Nothing selected -> do nothing.\n");
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}
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for (auto &it : submodules)
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handle_submodule(it.second);
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}
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};
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struct SubmodPass : public Pass {
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SubmodPass() : Pass("submod", "moving part of a module to a new submodule") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" submod [options] [selection]\n");
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log("\n");
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log("This pass identifies all cells with the 'submod' attribute and moves them to\n");
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log("a newly created module. The value of the attribute is used as name for the\n");
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log("cell that replaces the group of cells with the same attribute value.\n");
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log("\n");
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log("This pass can be used to create a design hierarchy in flat design. This can\n");
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log("be useful for analyzing or reverse-engineering a design.\n");
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log("\n");
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log("This pass only operates on completely selected modules with no processes\n");
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log("or memories.\n");
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log("\n");
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log(" -copy\n");
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log(" by default the cells are 'moved' from the source module and the source\n");
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log(" module will use an instance of the new module after this command is\n");
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log(" finished. call with -copy to not modify the source module.\n");
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log("\n");
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log(" -name <name>\n");
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log(" don't use the 'submod' attribute but instead use the selection. only\n");
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log(" objects from one module might be selected. the value of the -name option\n");
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log(" is used as the value of the 'submod' attribute instead.\n");
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log("\n");
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log(" -hidden\n");
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log(" instead of creating submodule ports with public names, create ports with\n");
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log(" private names so that a subsequent 'flatten; clean' call will restore the\n");
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log(" original module with original public names.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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log_header(design, "Executing SUBMOD pass (moving cells to submodules as requested).\n");
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log_push();
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std::string opt_name;
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bool copy_mode = false;
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bool hidden_mode = false;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-name" && argidx+1 < args.size()) {
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opt_name = args[++argidx];
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continue;
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}
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if (args[argidx] == "-copy") {
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copy_mode = true;
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continue;
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}
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if (args[argidx] == "-hidden") {
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hidden_mode = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (opt_name.empty())
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{
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Pass::call(design, "opt_clean");
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log_header(design, "Continuing SUBMOD pass.\n");
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std::set<RTLIL::IdString> handled_modules;
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bool did_something = true;
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while (did_something) {
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did_something = false;
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std::vector<RTLIL::IdString> queued_modules;
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for (auto &mod_it : design->modules_)
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if (handled_modules.count(mod_it.first) == 0 && design->selected_whole_module(mod_it.first))
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queued_modules.push_back(mod_it.first);
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for (auto &modname : queued_modules)
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if (design->modules_.count(modname) != 0) {
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SubmodWorker worker(design, design->modules_[modname], copy_mode, hidden_mode);
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handled_modules.insert(modname);
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did_something = true;
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}
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}
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Pass::call(design, "opt_clean");
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}
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else
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{
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RTLIL::Module *module = NULL;
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for (auto &mod_it : design->modules_) {
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if (!design->selected_module(mod_it.first))
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continue;
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if (module != NULL)
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log_cmd_error("More than one module selected: %s %s\n", module->name.c_str(), mod_it.first.c_str());
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module = mod_it.second;
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}
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if (module == NULL)
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log("Nothing selected -> do nothing.\n");
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else {
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Pass::call_on_module(design, module, "opt_clean");
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log_header(design, "Continuing SUBMOD pass.\n");
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SubmodWorker worker(design, module, copy_mode, hidden_mode, opt_name);
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}
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}
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log_pop();
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}
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} SubmodPass;
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PRIVATE_NAMESPACE_END
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