mirror of https://github.com/YosysHQ/yosys.git
12 lines
462 B
Bash
12 lines
462 B
Bash
#!/bin/bash
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set -ex
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sed 's/SB_MAC16/SB_MAC16_UUT/; /SB_MAC16_UUT/,/endmodule/ p; d;' < ../cells_sim.v > test_dsp_model_uut.v
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cat /opt/lscc/iCEcube2.2017.01/verilog/sb_ice_syn.v > test_dsp_model_ref.v
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for tb in testbench \
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testbench_comb_8x8_A testbench_comb_8x8_B testbench_comb_16x16 \
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testbench_seq_16x16_A testbench_seq_16x16_B
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do
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iverilog -s $tb -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v
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vvp -N ./test_dsp_model
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done
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