mirror of https://github.com/YosysHQ/yosys.git
135 lines
3.6 KiB
BibTeX
135 lines
3.6 KiB
BibTeX
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@misc{YosysGit,
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author = {Clifford Wolf},
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title = {{Yosys Open SYnthesis Suite (YOSYS)}},
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note = {\url{http://github.com/cliffordwolf/yosys}}
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}
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@misc{YosysTestsGit,
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author = {Clifford Wolf},
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title = {{Yosys Test Bench}},
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note = {\url{http://github.com/cliffordwolf/yosys-tests}}
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}
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@misc{VlogHammer,
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author = {Clifford Wolf},
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title = {{VlogHammer Verilog Synthesis Regression Tests}},
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note = {\url{http://github.com/cliffordwolf/VlogHammer}}
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}
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@misc{Icarus,
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author = {Stephen Williams},
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title = {{Icarus Verilog}},
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note = {Version 0.8.7, \url{http://iverilog.icarus.com/}}
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}
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@misc{VTR,
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author= {Jonathan Rose and Jason Luu and Chi Wai Yu and Opal Densmore and Jeff Goeders and Andrew Somerville and Kenneth B. Kent and Peter Jamieson and Jason Anderson},
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title = {{The Verilog-to-Routing (VTR) Project for FPGAs}},
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note = {Version 1.0, \url{https://code.google.com/p/vtr-verilog-to-routing/}}
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}
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@misc{HANA,
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author = {Parvez Ahmad},
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title = {{HDL Analyzer and Netlist Architect (HANA)}},
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note = {Verison linux64-1.0-alpha (2012-10-14), \url{http://sourceforge.net/projects/sim-sim/}}
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}
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@misc{MVSIS,
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author = {MVSIS group at Berkeley studies logic synthesis and verification for VLSI design},
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title = {{MVSIS: Logic Synthesis and Verification}},
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note = {Version 3.0, \url{http://embedded.eecs.berkeley.edu/mvsis/}}
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}
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@misc{VIS,
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author = {{The VIS group}},
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title = {{VIS: A system for Verification and Synthesis}},
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note = {Version 2.4, \url{http://vlsi.colorado.edu/~vis/}}
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}
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@misc{ABC,
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author = {{Berkeley Logic Synthesis and Verification Group}},
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title = {{ABC: A System for Sequential Synthesis and Verification}},
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note = {HQ Rev b5750272659f, 2012-10-28, \url{http://www.eecs.berkeley.edu/~alanmi/abc/}}
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}
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@misc{AIGER,
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author = {{Armin Biere, Johannes Kepler University Linz, Austria}},
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title = {{AIGER}},
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note = {\url{http://fmv.jku.at/aiger/}}
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}
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@misc{XilinxWebPACK,
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author = {{Xilinx, Inc.}},
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title = {{ISE WebPACK Design Software}},
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note = {\url{http://www.xilinx.com/products/design-tools/ise-design-suite/ise-webpack.htm}}
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}
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@misc{QuartusWeb,
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author = {{Altera, Inc.}},
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title = {{Quartus II Web Edition Software}},
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note = {\url{http://www.altera.com/products/software/quartus-ii/web-edition/qts-we-index.html}}
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}
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@misc{OR1200,
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title = {{OpenRISC 1200 CPU}},
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note = {\url{http://opencores.org/or1k/OR1200\_OpenRISC\_Processor}}
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}
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@misc{openMSP430,
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title = {{openMSP430 CPU}},
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note = {\url{http://opencores.org/project,openmsp430}}
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}
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@misc{i2cmaster,
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title = {{OpenCores I$^2$C Core}},
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note = {\url{http://opencores.org/project,i2c}}
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}
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@misc{k68,
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title = {{OpenCores k68 Core}},
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note = {\url{http://opencores.org/project,k68}}
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}
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@misc{bison,
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title = {{GNU Bison}},
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note = {\url{http://www.gnu.org/software/bison/}}
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}
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@misc{flex,
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title = {{Flex}},
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note = {\url{http://flex.sourceforge.net/}}
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}
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@misc{C_to_Verilog,
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title = {{C-to-Verilog}},
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note = {\url{http://www.c-to-verilog.com/}}
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}
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@misc{LegUp,
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title = {{LegUp}},
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note = {\url{http://legup.eecg.utoronto.ca/}}
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}
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@misc{LibertyFormat,
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title = {{The Liberty Library Modeling Standard}},
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note = {\url{http://www.opensourceliberty.org/}}
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}
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@misc{ASIC-WORLD,
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title = {{World of ASIC}},
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note = {\url{http://www.asic-world.com/}}
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}
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@misc{Formality,
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title = {{Synopsys Formality Equivalence Checking}},
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note = {\url{http://www.synopsys.com/Tools/Verification/FormalEquivalence/Pages/Formality.aspx}},
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}
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@misc{bigint,
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author = {Matt McCutchen},
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title = {{C++ Big Integer Library}},
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note = {\url{http://mattmccutchen.net/bigint/}}
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}
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