yosys/techlibs
Clifford Wolf 41555cde10 Reorganized stdcells.v (no actual code change, just moved and indented stuff) 2014-07-31 02:21:06 +02:00
..
cmos Added test comments to techlibs/cmos/cmos_cells.lib 2014-01-29 10:51:02 +01:00
common Reorganized stdcells.v (no actual code change, just moved and indented stuff) 2014-07-31 02:21:06 +02:00
xilinx Added "make PRETTY=1" 2014-07-24 17:15:01 +02:00
.gitignore added .gitignore files 2013-01-05 11:19:11 +01:00