mirror of https://github.com/YosysHQ/yosys.git
139 lines
4.4 KiB
Bash
139 lines
4.4 KiB
Bash
#!/bin/bash
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if [ $# -eq 0 ]; then
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echo "Usage: $0 <job_id>" >&2
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exit 1
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fi
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job="$1"
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set --
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set -ex
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rm -rf report_temp/$job
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mkdir -p report report_temp/$job
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cd report_temp/$job
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cp ../../vivado/$job.v syn_vivado.v
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cp ../../quartus/$job.v syn_quartus.v
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cp ../../xst/$job.v syn_xst.v
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cp ../../rtl/$job.v rtl.v
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yosys -p 'hierarchy; proc; opt; techmap; abc; opt' -b 'verilog -noattr' -o syn_yosys.v ../../rtl/$job.v
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cat ../../xl_cells.v ../../cy_cells.v > cells.v
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{
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echo "module ${job}_test(a, b, y1, y2);"
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sed -r '/^(input|output) / !d; /output/ { s/ y;/ y1;/; p; }; s/ y1;/ y2;/;' rtl.v
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echo "${job}_1 uut1 (.a(a), .b(b), .y(y1));"
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echo "${job}_2 uut2 (.a(a), .b(b), .y(y2));"
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echo "endmodule"
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} > test.v
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echo -n > fail_patterns.txt
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for p in syn_vivado syn_quartus syn_xst syn_yosys rtl; do
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for q in syn_vivado syn_quartus syn_xst syn_yosys rtl; do
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{
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echo "read_verilog -DGLBL $p.v"
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echo "rename $job ${job}_1"
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echo "read_verilog -DGLBL $q.v"
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echo "rename $job ${job}_2"
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echo "read_verilog cells.v test.v"
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echo "hierarchy -top ${job}_test"
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echo "proc; opt; flatten ${job}_test"
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echo "hierarchy -check -top ${job}_test"
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echo "! touch test.$p.$q.input_ok"
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echo "sat -timeout 60 -verify-no-timeout -show a,b,y1,y2 -prove y1 y2 ${job}_test"
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} > test.$p.$q.ys
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if yosys -l test.$p.$q.log test.$p.$q.ys; then
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echo PASS > result.${p}.${q}.txt
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else
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echo $( grep '^ *\\[ab] ' test.$p.$q.log | gawk '{ print $4; }' | tr -d '\n' ) >> fail_patterns.txt
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echo FAIL > result.${p}.${q}.txt
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fi
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# this fails if an error was encountered before the 'sat' command
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rm test.$p.$q.input_ok
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done; done
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{
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echo "module testbench;"
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sed -r '/^input / !d; s/^input/reg/;' rtl.v
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for p in syn_vivado syn_quartus syn_xst syn_yosys rtl; do
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sed -r "/^output / !d; s/^output/wire/; s/ y;/ ${p}_y;/;" rtl.v
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echo "${job}_${p} uut_${p} (.a(a), .b(b), .y(${p}_y));"
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done
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echo "initial begin"
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bits=$( echo $( grep '^input' rtl.v | cut -f2 -d'[' | cut -f1 -d: | tr '\n' '+' )2 | bc; )
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for pattern in $bits\'b0 ~$bits\'b0 $( sed "s/^/$bits'b/;" < fail_patterns.txt ); do
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echo " { a, b } <= $pattern; #1;"
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for p in syn_vivado syn_quartus syn_xst syn_yosys rtl; do
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echo " \$display(\"++RPT++ %b $p\", ${p}_y);"
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done
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echo " \$display(\"++RPT++ ----\");"
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done
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echo "end"
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echo "endmodule"
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for p in syn_vivado syn_quartus syn_xst syn_yosys rtl; do
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sed "s/^module ${job}/module ${job}_${p}/; /^\`timescale/ d;" < $p.v
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done
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cat cells.v
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} > testbench.v
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/opt/altera/13.0/modelsim_ase/bin/vlib work
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/opt/altera/13.0/modelsim_ase/bin/vlog testbench.v
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/opt/altera/13.0/modelsim_ase/bin/vsim -c -do "run; exit" work.testbench | tee sim_modelsim.log
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. /opt/Xilinx/14.5/ISE_DS/settings64.sh
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vlogcomp testbench.v
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fuse -o testbench testbench
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{ echo "run all"; echo "exit"; } > run-all.tcl
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./testbench -tclbatch run-all.tcl | tee sim_isim.log
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for p in syn_vivado syn_quartus syn_xst syn_yosys rtl; do
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for q in isim modelsim; do
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echo $( grep '++RPT++' sim_$q.log | sed 's,.*++RPT++ ,,' | grep " $p\$" | gawk '{ print $1; }' | md5sum | gawk '{ print $1; }' ) > result.${p}.${q}.txt
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done; done
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echo "#00ff00" > color_PASS.txt
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echo "#ff0000" > color_FAIL.txt
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{
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echo "<h3>Hammer Report: $job</h3>"
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echo "<table border>"
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echo "<tr><th width=\"100\"></th>"
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for q in syn_vivado syn_quartus syn_xst syn_yosys rtl isim modelsim; do
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echo "<th width=\"100\">$q</th>"
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done
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echo "</tr>"
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for p in syn_vivado syn_quartus syn_xst syn_yosys rtl; do
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echo "<tr><th>$p</th>"
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for q in syn_vivado syn_quartus syn_xst syn_yosys rtl isim modelsim; do
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read result < result.${p}.${q}.txt
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if ! test -f color_$result.txt; then
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case $( ls color_*.txt | wc -l ) in
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2) echo "#ffff00" > color_$result.txt ;;
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3) echo "#ff00ff" > color_$result.txt ;;
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4) echo "#00ffff" > color_$result.txt ;;
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*) echo "#888888" > color_$result.txt ;;
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esac
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fi
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echo "<td align=\"center\" bgcolor=\"$( cat color_$result.txt )\">$( echo $result | cut -c1-8 )</td>"
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done
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echo "</tr>"
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done
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echo "<tr><td colspan=\"8\"><pre>$( perl -pe 's/([<>&])/"&#".ord($1).";"/eg;' rtl.v |
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perl -pe 's!([^\w#]|^)(\w+)\b!$x = $1; $y = $2; sprintf("%s<span style=\"color: %s;\">%s</span>", $x, $y =~ /module|input|wire|output|assign|signed|endmodule/ ? "#008800;" : "#000088;", $y)!eg' )</pre></td></tr>"
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#perl -pe 's,\b(module|input|wire|output|assign|signed|endmodule)\b,<span style="color: #008800;">$1</span>,g' )</pre></td></tr>"
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echo "</table>"
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} > ../../report/$job.html
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