This website requires JavaScript.
Explore
Help
Sign In
riscv
/
yosys
mirror of
https://github.com/YosysHQ/yosys.git
Watch
1
Star
0
Fork
You've already forked yosys
0
Code
Issues
Projects
Releases
Wiki
Activity
3fd37061bf
yosys
/
tests
/
hana
/
test_simulation_inc_32_test.v
6 lines
79 B
Verilog
Raw
Blame
History
module
test
(
input
[
31
:
0
]
in
,
output
[
31
:
0
]
out
)
;
assign
out
=
-
in
;
endmodule
Reference in New Issue
View Git Blame
Copy Permalink