This website requires JavaScript.
Explore
Help
Sign In
riscv
/
yosys
mirror of
https://github.com/YosysHQ/yosys.git
Watch
1
Star
0
Fork
You've already forked yosys
0
Code
Issues
Projects
Releases
Wiki
Activity
3fd37061bf
yosys
/
tests
/
hana
/
test_simulation_and_3_test.v
4 lines
87 B
Verilog
Raw
Blame
History
module
test
(
input
[
2
:
0
]
in
,
output
out
)
;
assign
out
=
in
[
0
]
&
in
[
1
]
&
in
[
2
]
;
endmodule
Reference in New Issue
View Git Blame
Copy Permalink