mirror of https://github.com/YosysHQ/yosys.git
78 lines
2.3 KiB
Plaintext
78 lines
2.3 KiB
Plaintext
pattern ql_dsp_macc
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// Rough sketch: (mux is optional)
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//
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// /-----------------------\
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// | |
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// \ / |
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// mul ----> add -----> mux -----> ff -+---->
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// | /\
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// | |
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// --------------
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state <IdString> add_ba
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state <IdString> mux_ab
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// Is the output taken from before or after the FF?
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state <bool> output_registered
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// Is there a mux in the pattern?
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state <bool> mux_in_pattern
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code mux_in_pattern
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mux_in_pattern = false;
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branch;
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mux_in_pattern = true;
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endcode
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// The multiplier is at the center of our pattern
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match mul
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select mul->type.in($mul)
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// It has either two or three consumers depending on whether there's a mux
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// in the pattern or not
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select nusers(port(mul, \Y)) <= 3
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filter nusers(port(mul, \Y)) == (mux_in_pattern ? 3 : 2)
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endmatch
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code output_registered
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output_registered = false;
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branch;
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output_registered = true;
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endcode
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match add
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select add->type.in($add, $sub)
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choice <IdString> AB {\A, \B}
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define <IdString> BA (AB == \A ? \B : \A)
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// One input to the adder is fed by the multiplier
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index <SigSpec> port(add, AB) === port(mul, \Y)
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// Save the other input port, it needs to be fed by the flip-flop
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set add_ba BA
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// Adder has either two or three consumers; it will have three consumers
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// IFF there's no mux in the pattern and the multiplier-accumulator result
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// is taken unregistered
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filter nusers(port(add, \Y)) == (!mux_in_pattern && !output_registered ? 3 : 2)
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endmatch
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match mux
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if mux_in_pattern
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select mux->type.in($mux)
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choice <IdString> AB {\A, \B}
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define <IdString> BA (AB == \A ? \B : \A)
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index <SigSpec> port(mux, AB) === port(mul, \Y)
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index <SigSpec> port(mux, BA) === port(add, \Y)
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filter nusers(port(mux, \Y)) == (output_registered ? 2 : 3)
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set mux_ab AB
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endmatch
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match ff
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select ff->type.in($dff, $adff, $dffe, $adffe)
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select param(ff, \CLK_POLARITY).as_bool()
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index <SigSpec> port(ff, \D) === mux_in_pattern ? port(mux, \Y) : port(add, \Y);
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index <SigSpec> port(ff, \Q) === port(add, add_ba)
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filter nusers(port(ff, \Q)) == (output_registered ? 3 : 2)
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endmatch
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code
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accept;
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endcode
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