mirror of https://github.com/YosysHQ/yosys.git
302 lines
8.3 KiB
C++
302 lines
8.3 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/celltypes.h"
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#include "kernel/log.h"
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#include "kernel/register.h"
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#include "kernel/rtlil.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct SynthPass : public ScriptPass {
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SynthPass() : ScriptPass("synth", "generic synthesis script") {}
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" synth [options]\n");
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log("\n");
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log("This command runs the default synthesis script. This command does not operate\n");
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log("on partly selected designs.\n");
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log("\n");
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log(" -top <module>\n");
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log(" use the specified module as top module (default='top')\n");
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log("\n");
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log(" -auto-top\n");
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log(" automatically determine the top of the design hierarchy\n");
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log("\n");
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log(" -flatten\n");
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log(" flatten the design before synthesis. this will pass '-auto-top' to\n");
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log(" 'hierarchy' if no top module is specified.\n");
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log("\n");
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log(" -encfile <file>\n");
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log(" passed to 'fsm_recode' via 'fsm'\n");
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log("\n");
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log(" -lut <k>\n");
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log(" perform synthesis for a k-LUT architecture.\n");
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log("\n");
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log(" -nofsm\n");
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log(" do not run FSM optimization\n");
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log("\n");
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log(" -noabc\n");
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log(" do not run abc (as if yosys was compiled without ABC support)\n");
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log("\n");
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log(" -booth\n");
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log(" run the booth pass to convert $mul to Booth encoded multipliers");
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log("\n");
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log(" -noalumacc\n");
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log(" do not run 'alumacc' pass. i.e. keep arithmetic operators in\n");
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log(" their direct form ($add, $sub, etc.).\n");
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log("\n");
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log(" -nordff\n");
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log(" passed to 'memory'. prohibits merging of FFs into memory read ports\n");
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log("\n");
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log(" -noshare\n");
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log(" do not run SAT-based resource sharing\n");
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log("\n");
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log(" -run <from_label>[:<to_label>]\n");
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log(" only run the commands between the labels (see below). an empty\n");
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log(" from label is synonymous to 'begin', and empty to label is\n");
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log(" synonymous to the end of the command list.\n");
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log("\n");
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log(" -abc9\n");
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log(" use new ABC9 flow (EXPERIMENTAL)\n");
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log("\n");
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log(" -flowmap\n");
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log(" use FlowMap LUT techmapping instead of ABC\n");
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log("\n");
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log(" -no-rw-check\n");
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log(" marks all recognized read ports as \"return don't-care value on\n");
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log(" read/write collision\" (same result as setting the no_rw_check\n");
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log(" attribute on all memories).\n");
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log("\n");
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log("\n");
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log("The following commands are executed by this synthesis command:\n");
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help_script();
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log("\n");
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}
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string top_module, fsm_opts, memory_opts, abc;
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bool autotop, flatten, noalumacc, nofsm, noabc, noshare, flowmap, booth;
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int lut;
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void clear_flags() override
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{
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top_module.clear();
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fsm_opts.clear();
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memory_opts.clear();
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autotop = false;
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flatten = false;
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lut = 0;
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noalumacc = false;
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nofsm = false;
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noabc = false;
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noshare = false;
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flowmap = false;
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booth = false;
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abc = "abc";
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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string run_from, run_to;
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clear_flags();
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-top" && argidx + 1 < args.size()) {
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top_module = args[++argidx];
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continue;
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}
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if (args[argidx] == "-encfile" && argidx + 1 < args.size()) {
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fsm_opts = " -encfile " + args[++argidx];
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continue;
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}
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if (args[argidx] == "-run" && argidx + 1 < args.size()) {
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size_t pos = args[argidx + 1].find(':');
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if (pos == std::string::npos) {
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run_from = args[++argidx];
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run_to = args[argidx];
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} else {
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run_from = args[++argidx].substr(0, pos);
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run_to = args[argidx].substr(pos + 1);
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}
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continue;
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}
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if (args[argidx] == "-auto-top") {
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autotop = true;
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continue;
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}
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if (args[argidx] == "-flatten") {
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flatten = true;
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continue;
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}
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if (args[argidx] == "-lut") {
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lut = atoi(args[++argidx].c_str());
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continue;
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}
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if (args[argidx] == "-nofsm") {
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nofsm = true;
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continue;
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}
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if (args[argidx] == "-noabc") {
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noabc = true;
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continue;
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}
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if (args[argidx] == "-noalumacc") {
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noalumacc = true;
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continue;
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}
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if (args[argidx] == "-booth") {
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booth = true;
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continue;
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}
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if (args[argidx] == "-nordff") {
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memory_opts += " -nordff";
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continue;
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}
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if (args[argidx] == "-noshare") {
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noshare = true;
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continue;
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}
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if (args[argidx] == "-abc9") {
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abc = "abc9";
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continue;
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}
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if (args[argidx] == "-flowmap") {
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flowmap = true;
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continue;
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}
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if (args[argidx] == "-no-rw-check") {
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memory_opts += " -no-rw-check";
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (!design->full_selection())
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log_cmd_error("This command only operates on fully selected designs!\n");
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if (abc == "abc9" && !lut)
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log_cmd_error("ABC9 flow only supported for FPGA synthesis (using '-lut' option)\n");
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if (flowmap && !lut)
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log_cmd_error("FlowMap is only supported for FPGA synthesis (using '-lut' option)\n");
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log_header(design, "Executing SYNTH pass.\n");
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log_push();
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run_script(design, run_from, run_to);
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log_pop();
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}
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void script() override
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{
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if (check_label("begin")) {
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if (help_mode) {
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run("hierarchy -check [-top <top> | -auto-top]");
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} else {
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if (top_module.empty()) {
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if (flatten || autotop)
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run("hierarchy -check -auto-top");
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else
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run("hierarchy -check");
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} else
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run(stringf("hierarchy -check -top %s", top_module.c_str()));
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}
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}
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if (check_label("coarse")) {
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run("proc");
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if (help_mode || flatten)
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run("flatten", " (if -flatten)");
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run("opt_expr");
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run("opt_clean");
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run("check");
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run("opt -nodffe -nosdff");
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if (!nofsm)
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run("fsm" + fsm_opts, " (unless -nofsm)");
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run("opt");
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run("wreduce");
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run("peepopt");
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run("opt_clean");
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if (help_mode)
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run("techmap -map +/cmp2lut.v -map +/cmp2lcu.v", " (if -lut)");
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else if (lut)
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run(stringf("techmap -map +/cmp2lut.v -map +/cmp2lcu.v -D LUT_WIDTH=%d", lut));
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if (booth)
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run("booth");
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if (!noalumacc)
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run("alumacc", " (unless -noalumacc)");
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if (!noshare)
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run("share", " (unless -noshare)");
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run("opt");
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run("memory -nomap" + memory_opts);
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run("opt_clean");
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}
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if (check_label("fine")) {
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run("opt -fast -full");
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run("memory_map");
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run("opt -full");
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run("techmap");
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if (help_mode) {
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run("techmap -map +/gate2lut.v", "(if -noabc and -lut)");
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run("clean; opt_lut", " (if -noabc and -lut)");
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run("flowmap -maxlut K", " (if -flowmap and -lut)");
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} else if (noabc && lut) {
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run(stringf("techmap -map +/gate2lut.v -D LUT_WIDTH=%d", lut));
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run("clean; opt_lut");
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} else if (flowmap) {
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run(stringf("flowmap -maxlut %d", lut));
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}
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run("opt -fast");
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if (!noabc && !flowmap) {
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#ifdef YOSYS_ENABLE_ABC
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if (help_mode) {
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run(abc + " -fast", " (unless -noabc, unless -lut)");
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run(abc + " -fast -lut k", "(unless -noabc, if -lut)");
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} else {
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if (lut)
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run(stringf("%s -fast -lut %d", abc.c_str(), lut));
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else
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run(abc + " -fast");
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}
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run("opt -fast", " (unless -noabc)");
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#endif
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}
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}
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if (check_label("check")) {
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run("hierarchy -check");
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run("stat");
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run("check");
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}
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}
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} SynthPass;
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PRIVATE_NAMESPACE_END
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