mirror of https://github.com/YosysHQ/yosys.git
121 lines
3.7 KiB
C++
121 lines
3.7 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/rtlil.h"
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#include "kernel/log.h"
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static void rename_in_module(RTLIL::Module *module, std::string from_name, std::string to_name)
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{
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from_name = RTLIL::escape_id(from_name);
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to_name = RTLIL::escape_id(to_name);
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if (module->count_id(to_name))
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log_cmd_error("There is already an object `%s' in module `%s'.\n", to_name.c_str(), module->name.c_str());
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for (auto &it : module->wires)
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if (it.first == from_name) {
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RTLIL::Wire *wire = it.second;
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log("Renaming wire %s to %s in module %s.\n", wire->name.c_str(), to_name.c_str(), module->name.c_str());
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module->wires.erase(wire->name);
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wire->name = to_name;
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module->add(wire);
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return;
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}
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for (auto &it : module->cells)
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if (it.first == from_name) {
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RTLIL::Cell *cell = it.second;
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log("Renaming cell %s to %s in module %s.\n", cell->name.c_str(), to_name.c_str(), module->name.c_str());
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module->cells.erase(cell->name);
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cell->name = to_name;
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module->add(cell);
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return;
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}
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log_cmd_error("Object `%s' not found!\n", from_name.c_str());
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}
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struct RenamePass : public Pass {
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RenamePass() : Pass("rename", "rename object in the design") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" rename old_name new_name\n");
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log("\n");
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log("Rename the specified object. Note that selection patterns are not supported\n");
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log("by this command.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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bool flag_enumerate = false;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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std::string arg = args[argidx];
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//if (arg == "-enumerate") {
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// flag_enumerate = true;
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// continue;
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//}
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break;
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}
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if (flag_enumerate)
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{
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extra_args(args, argidx, design);
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log_cmd_error("Sorry: Enumeration mode is not implemented at the moment.\n");
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}
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else
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{
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if (argidx+2 != args.size())
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log_cmd_error("Invalid number of arguments!\n");
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std::string from_name = args[argidx++];
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std::string to_name = args[argidx++];
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if (!design->selected_active_module.empty())
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{
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if (design->modules.count(design->selected_active_module) > 0)
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rename_in_module(design->modules.at(design->selected_active_module), from_name, to_name);
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}
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else
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{
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for (auto &mod : design->modules) {
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if (mod.first == from_name || RTLIL::unescape_id(mod.first) == from_name) {
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to_name = RTLIL::escape_id(to_name);
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log("Renaming module %s to %s.\n", mod.first.c_str(), to_name.c_str());
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RTLIL::Module *module = mod.second;
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design->modules.erase(module->name);
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module->name = to_name;
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design->modules[module->name] = module;
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goto rename_ok;
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}
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}
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log_cmd_error("Object `%s' not found!\n", from_name.c_str());
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rename_ok:;
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}
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}
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}
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} RenamePass;
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