yosys/tests/techmap/han-carlson.tcl

15 lines
321 B
Tcl

yosys -import
read_verilog +/choices/han-carlson.v
read_verilog lcu_refined.v
design -save init
for {set i 1} {$i <= 16} {incr i} {
design -load init
chparam -set WIDTH $i
yosys proc
equiv_make -blacklist ppa.nomatch lcu _85_lcu_han_carlson equiv
equiv_simple equiv
equiv_status -assert equiv
}