yosys/passes
Clifford Wolf 9717495401 Fixed handling of inverters (aka 1-input luts) in nlutmap 2016-03-23 08:56:08 +01:00
..
cmds Support for abstract modules in chparam 2016-03-21 16:37:35 +01:00
equiv Added "equiv_struct -fwonly" 2016-01-08 10:59:16 +01:00
fsm Added "int ceil_log2(int)" function 2016-02-13 16:52:16 +01:00
hierarchy Cleanup abstract modules at end of "hierarchy -top" 2016-03-21 16:37:35 +01:00
memory Fixed some visual studio warnings 2016-02-13 17:31:24 +01:00
opt Use alphanumerical order instead of idstring idx in opt_clean compare_signals() 2016-02-02 09:16:18 +01:00
proc Improved proc_mux performance for huge always blocks 2015-12-02 22:02:20 +01:00
sat Import more std:: stuff into Yosys namespace 2015-10-25 19:30:49 +01:00
techmap Fixed handling of inverters (aka 1-input luts) in nlutmap 2016-03-23 08:56:08 +01:00
tests Import more std:: stuff into Yosys namespace 2015-10-25 19:30:49 +01:00