mirror of https://github.com/YosysHQ/yosys.git
35 lines
537 B
Verilog
35 lines
537 B
Verilog
module tb();
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reg clk;
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reg reset;
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reg enable;
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reg up_down;
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wire [7 : 0] count;
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wire overflow;
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initial begin
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$monitor("rst %b en %b updown %b cnt %b overflow %b",
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reset,enable,up_down,count, overflow);
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clk = 0;
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reset = 1;
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enable = 0;
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up_down = 0;
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#10 reset = 0;
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#1 enable = 1;
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#20 up_down = 1;
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#30 $finish;
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end
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always #1 clk = ~clk;
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lfsr_updown U(
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.clk ( clk ),
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.reset ( reset ),
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.enable ( enable ),
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.up_down ( up_down ),
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.count ( count ),
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.overflow ( overflow )
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);
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endmodule
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