mirror of https://github.com/YosysHQ/yosys.git
21 lines
382 B
Verilog
21 lines
382 B
Verilog
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module RAM64X1D (
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output DPO, SPO,
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input D, WCLK, WE,
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input A0, A1, A2, A3, A4, A5,
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input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
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);
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parameter INIT = 64'h0;
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parameter IS_WCLK_INVERTED = 1'b0;
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endmodule
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module RAM128X1D (
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output DPO, SPO,
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input D, WCLK, WE,
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input [6:0] A, DPRA
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);
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parameter INIT = 128'h0;
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parameter IS_WCLK_INVERTED = 1'b0;
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endmodule
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